From owner-p4-projects@FreeBSD.ORG Sun Mar 1 09:57:32 2009 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id EF8FB10656DD; Sun, 1 Mar 2009 09:57:31 +0000 (UTC) Delivered-To: perforce@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 9310510656DA for ; Sun, 1 Mar 2009 09:57:31 +0000 (UTC) (envelope-from lulf@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 80CBF8FC1A for ; Sun, 1 Mar 2009 09:57:31 +0000 (UTC) (envelope-from lulf@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n219vVLv064823 for ; Sun, 1 Mar 2009 09:57:31 GMT (envelope-from lulf@FreeBSD.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n219vVk1064821 for perforce@freebsd.org; Sun, 1 Mar 2009 09:57:31 GMT (envelope-from lulf@FreeBSD.org) Date: Sun, 1 Mar 2009 09:57:31 GMT Message-Id: <200903010957.n219vVk1064821@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to lulf@FreeBSD.org using -f From: Ulf Lilleengen To: Perforce Change Reviews Cc: Subject: PERFORCE change 158521 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 01 Mar 2009 09:57:33 -0000 http://perforce.freebsd.org/chv.cgi?CH=158521 Change 158521 by lulf@lulf_carrot on 2009/03/01 09:57:00 - Implement cache handling used by busdma. Affected files ... .. //depot/projects/avr32/src/sys/avr32/avr32/cache.c#2 edit Differences ... ==== //depot/projects/avr32/src/sys/avr32/avr32/cache.c#2 (text+ko) ==== @@ -41,9 +41,24 @@ #include #include -/* TODO: - - Implement l1 cache handling. -*/ +/* Valid cache op codes. */ +#define ICACHE_INVALIDATE 0x01 +#define DCACHE_INVALIDATE 0x0b +#define DCACHE_WRITEBACK 0x0c +#define DCACHE_WRITEBACK_INVALIDATE 0x0d + +/* Next line boundary. */ +#define round_line(va, size) (((va) + ((size) - 1)) & ~((size) - 1)) +/* Previous line boundary. */ +#define trunc_line(va, size) ((va) & ~((size) - 1)) + +/* Perform operation on cache line. */ +#define cache_line_op(va, op) \ + __asm__ __volatile( \ + "cache %0[0], %1" \ + : \ + : "r" (va), "n" (op) \ + : "memory") struct avr32_cache_ops avr32_cache_ops; @@ -58,14 +73,14 @@ void avr32_nocache_wb_range(vm_offset_t, vm_size_t); /* For l1 cache. */ -void avr32_l1cache_sync_all(void); -void avr32_l1cache_sync_range(vm_offset_t, vm_size_t); -void avr32_l1cache_sync_range_index(vm_offset_t, vm_size_t); -void avr32_l1cache_wbinv_all(void); -void avr32_l1cache_wbinv_range(vm_offset_t, vm_size_t); -void avr32_l1cache_wbinv_range_index(vm_offset_t, vm_size_t); -void avr32_l1cache_inv_range(vm_offset_t, vm_size_t); -void avr32_l1cache_wb_range(vm_offset_t, vm_size_t); +void avr32_l1icache_sync_all(void); +void avr32_l1icache_sync_range(vm_offset_t, vm_size_t); +void avr32_l1icache_sync_range_index(vm_offset_t, vm_size_t); +void avr32_l1dcache_wbinv_all(void); +void avr32_l1dcache_wbinv_range(vm_offset_t, vm_size_t); +void avr32_l1dcache_wbinv_range_index(vm_offset_t, vm_size_t); +void avr32_l1dcache_inv_range(vm_offset_t, vm_size_t); +void avr32_l1dcache_wb_range(vm_offset_t, vm_size_t); u_int avr32_icache_size; u_int avr32_icache_line_size; @@ -116,11 +131,11 @@ avr32_cache_ops.mco_icache_sync_range_index = avr32_nocache_sync_range_index; } else { - avr32_cache_ops.mco_icache_sync_all = avr32_l1cache_sync_all; + avr32_cache_ops.mco_icache_sync_all = avr32_l1icache_sync_all; avr32_cache_ops.mco_icache_sync_range = - avr32_l1cache_sync_range; + avr32_l1icache_sync_range; avr32_cache_ops.mco_icache_sync_range_index = - avr32_l1cache_sync_range_index; + avr32_l1icache_sync_range_index; } if (avr32_dcache_line_size == 1) { @@ -132,13 +147,13 @@ avr32_cache_ops.mco_dcache_inv_range = avr32_nocache_inv_range; avr32_cache_ops.mco_dcache_wb_range = avr32_nocache_wb_range; } else { - avr32_cache_ops.mco_dcache_wbinv_all = avr32_l1cache_wbinv_all; + avr32_cache_ops.mco_dcache_wbinv_all = avr32_l1dcache_wbinv_all; avr32_cache_ops.mco_dcache_wbinv_range = - avr32_l1cache_wbinv_range; + avr32_l1dcache_wbinv_range; avr32_cache_ops.mco_dcache_wbinv_range_index = - avr32_l1cache_wbinv_range_index; - avr32_cache_ops.mco_dcache_inv_range = avr32_l1cache_inv_range; - avr32_cache_ops.mco_dcache_wb_range = avr32_l1cache_wb_range; + avr32_l1dcache_wbinv_range_index; + avr32_cache_ops.mco_dcache_inv_range = avr32_l1dcache_inv_range; + avr32_cache_ops.mco_dcache_wb_range = avr32_l1dcache_wb_range; } } @@ -155,35 +170,77 @@ /* Operations for l1 cache. */ void -avr32_l1cache_sync_all(void) +avr32_l1icache_sync_all(void) { + avr32_impl(); } void -avr32_l1cache_sync_range(vm_offset_t from, vm_size_t size) +avr32_l1icache_sync_range(vm_offset_t from, vm_size_t size) { + avr32_impl(); } void -avr32_l1cache_sync_range_index(vm_offset_t from, vm_size_t size) -{} +avr32_l1icache_sync_range_index(vm_offset_t from, vm_size_t size) +{ + avr32_impl(); +} void -avr32_l1cache_wbinv_all(void) -{} +avr32_l1dcache_wbinv_all(void) +{ + avr32_impl(); +} void -avr32_l1cache_wbinv_range(vm_offset_t from, vm_size_t size) -{} +avr32_l1dcache_wbinv_range_index(vm_offset_t from, vm_size_t size) +{ + avr32_impl(); +} void -avr32_l1cache_wbinv_range_index(vm_offset_t from, vm_size_t size) -{} +avr32_l1dcache_wbinv_range(vm_offset_t from, vm_size_t size) +{ + vm_offset_t va, va_end; + + /* Put address at a cache line boundary. */ + va = trunc_line(from, avr32_dcache_line_size); + va_end = round_line(from + size, avr32_dcache_line_size); + + while (va < va_end) { + cache_line_op(va, DCACHE_WRITEBACK_INVALIDATE); + va += avr32_dcache_line_size; + } +} + void -avr32_l1cache_inv_range(vm_offset_t from, vm_size_t size) -{} +avr32_l1dcache_inv_range(vm_offset_t from, vm_size_t size) +{ + vm_offset_t va, va_end; + + /* Put address at a cache line boundary. */ + va = trunc_line(from, avr32_dcache_line_size); + va_end = round_line(from + size, avr32_dcache_line_size); + + while (va < va_end) { + cache_line_op(va, DCACHE_INVALIDATE); + va += avr32_dcache_line_size; + } +} void -avr32_l1cache_wb_range(vm_offset_t from, vm_size_t size) -{} +avr32_l1dcache_wb_range(vm_offset_t from, vm_size_t size) +{ + vm_offset_t va, va_end; + + /* Put address at a cache line boundary. */ + va = trunc_line(from, avr32_dcache_line_size); + va_end = round_line(from + size, avr32_dcache_line_size); + + while (va < va_end) { + cache_line_op(va, DCACHE_WRITEBACK); + va += avr32_dcache_line_size; + } +}