From owner-svn-src-all@freebsd.org Mon Sep 11 20:41:27 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 39372E23272; Mon, 11 Sep 2017 20:41:27 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 06FC471EA0; Mon, 11 Sep 2017 20:41:26 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v8BKfQIY020775; Mon, 11 Sep 2017 20:41:26 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v8BKfQbv020774; Mon, 11 Sep 2017 20:41:26 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201709112041.v8BKfQbv020774@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: Conrad Meyer Date: Mon, 11 Sep 2017 20:41:26 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r323462 - head/sys/x86/x86 X-SVN-Group: head X-SVN-Commit-Author: cem X-SVN-Commit-Paths: head/sys/x86/x86 X-SVN-Commit-Revision: 323462 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 11 Sep 2017 20:41:27 -0000 Author: cem Date: Mon Sep 11 20:41:25 2017 New Revision: 323462 URL: https://svnweb.freebsd.org/changeset/base/323462 Log: x86 MCA: Extract CMCI support predicate into function On AMD, the MCG_CAP feature bit is reserved -- not explicitly zero. Do not use it to determine CMCI support. Reviewed by: avg, markj Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12320 Modified: head/sys/x86/x86/mca.c Modified: head/sys/x86/x86/mca.c ============================================================================== --- head/sys/x86/x86/mca.c Mon Sep 11 20:33:20 2017 (r323461) +++ head/sys/x86/x86/mca.c Mon Sep 11 20:41:25 2017 (r323462) @@ -149,6 +149,18 @@ amd_thresholding_supported(void) } #endif +static inline bool +cmci_supported(uint64_t mcg_cap) +{ + /* + * MCG_CAP_CMCI_P bit is reserved in AMD documentation. Until + * it is defined, do not use it to check for CMCI support. + */ + if (cpu_vendor_id != CPU_VENDOR_INTEL) + return (false); + return ((mcg_cap & MCG_CAP_CMCI_P) != 0); +} + static int sysctl_positive_int(SYSCTL_HANDLER_ARGS) { @@ -322,7 +334,7 @@ mca_log(const struct mca_record *rec) printf("UNCOR "); else { printf("COR "); - if (rec->mr_mcg_cap & MCG_CAP_CMCI_P) + if (cmci_supported(rec->mr_mcg_cap)) printf("(%lld) ", ((long long)rec->mr_status & MC_STATUS_COR_COUNT) >> 38); } @@ -873,7 +885,7 @@ mca_setup(uint64_t mcg_cap) "force_scan", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, 0, sysctl_mca_scan, "I", "Force an immediate scan for machine checks"); #ifdef DEV_APIC - if (mcg_cap & MCG_CAP_CMCI_P) + if (cmci_supported(mcg_cap)) cmci_setup(); else if (amd_thresholding_supported()) amd_thresholding_setup(); @@ -1104,7 +1116,7 @@ _mca_init(int boot) wrmsr(MSR_MC_CTL(i), ctl); #ifdef DEV_APIC - if (mcg_cap & MCG_CAP_CMCI_P) { + if (cmci_supported(mcg_cap)) { if (boot) cmci_monitor(i); else