From owner-freebsd-arm@FreeBSD.ORG Tue Mar 24 21:26:17 2009 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8B7631065754 for ; Tue, 24 Mar 2009 21:26:16 +0000 (UTC) (envelope-from mlfbsd@dong.ci0.org) Received: from dong.ci0.org (dong.ci0.org [IPv6:2001:7a8:2066:1::1]) by mx1.freebsd.org (Postfix) with ESMTP id B0B698FC13 for ; Tue, 24 Mar 2009 21:26:14 +0000 (UTC) (envelope-from mlfbsd@dong.ci0.org) Received: from dong.ci0.org (localhost.ci0.org [127.0.0.1]) by dong.ci0.org (8.14.1/8.13.8) with ESMTP id n2P0Gpmd084771; Wed, 25 Mar 2009 01:16:51 +0100 (CET) (envelope-from mlfbsd@dong.ci0.org) Received: (from mlfbsd@localhost) by dong.ci0.org (8.14.1/8.13.8/Submit) id n2P0GoqD084770; Wed, 25 Mar 2009 01:16:50 +0100 (CET) (envelope-from mlfbsd) Date: Wed, 25 Mar 2009 01:16:49 +0100 From: Olivier Houchard To: Mark Tinguely Message-ID: <20090325001649.GA84198@ci0.org> References: <200903242105.n2OL5phe074750@casselton.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200903242105.n2OL5phe074750@casselton.net> User-Agent: Mutt/1.4.1i Cc: freebsd-arm@freebsd.org Subject: Re: ARM atomic question X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Mar 2009 21:26:18 -0000 Hi Mark, On Tue, Mar 24, 2009 at 04:05:51PM -0500, Mark Tinguely wrote: > > I am rewriting the existing ARM atomic instruction for the new ldrex/strex > in the ARMv6 architecture. > That's great. I really want to get armv6 support. > I have 3 questions for atomic_fetchadd_32(): > > #ifdef KERNEL > static __inline uint32_t > atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) > { > uint32_t value; > > __with_interrupts_disabled( > { > value = *p; > *p += v; > }); > return (value); > } > > #else /* !_KERNEL */ > > static __inline uint32_t > atomic_fetchadd_32(volatile uint32_t *p, uint32_t v) > { > uint32_t start, ras_start = ARM_RAS_START; > > __asm __volatile("1:\n" > "adr %1, 1b\n" > "str %1, [%0]\n" > "adr %1, 2f\n" > "str %1, [%0, #4]\n" > "ldr %1, [%2]\n" > > 1) how does this make it atomic? no one reads ras_start or ras_end > to verify that it has not changed since I set it. This applies > to all non-kernel atomic commands. > It is done by the kernel, when a trap occurs. They are issues with that code, though, which should be worked on. > "add %1, %1, %3\n" > ^^ > 2) start is now (*p + v) not *p. It will return the wrong value > compared to the kernel version. > True, that's a bug. > "str %0, [%2]\n" > ^^ > 3) *p is assigned the ras_start address. > Another bug. Guess we've been lucky not to run into it. Thanks ! > "2:\n" > "mov %3, #0\n" > "str %3, [%0]\n" > "mov %3, #0xffffffff\n" > "str %3, [%0, #4]\n" > : "+r" (ras_start), "=r" (start), "+r" (p), "+r" (v) > : : "memory"); > return (start); > #endif > > 4) Is there a list of atomic commands that should be implemented? > All those described in atomic(9) (except 64bits operations). Regards, Olivier