From owner-freebsd-arm@FreeBSD.ORG Sun Mar 3 19:43:31 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by hub.freebsd.org (Postfix) with ESMTP id 9D3A6916 for ; Sun, 3 Mar 2013 19:43:31 +0000 (UTC) (envelope-from kientzle@freebsd.org) Received: from monday.kientzle.com (99-115-135-74.uvs.sntcca.sbcglobal.net [99.115.135.74]) by mx1.freebsd.org (Postfix) with ESMTP id 64C2D657 for ; Sun, 3 Mar 2013 19:43:30 +0000 (UTC) Received: (from root@localhost) by monday.kientzle.com (8.14.4/8.14.4) id r23JhON3066497 for freebsd-arm@freebsd.org; Sun, 3 Mar 2013 19:43:24 GMT (envelope-from kientzle@freebsd.org) Received: from [192.168.2.143] (CiscoE3000 [192.168.1.65]) by kientzle.com with SMTP id cyx5aui9ib5guycd2brwgnzdbs; for freebsd-arm@freebsd.org; Sun, 03 Mar 2013 19:43:24 +0000 (UTC) (envelope-from kientzle@freebsd.org) From: Tim Kientzle Content-Type: multipart/signed; boundary="Apple-Mail=_F90B5CAF-B0AA-4609-AF80-4A91CA3659E3"; protocol="application/pgp-signature"; micalg=pgp-sha1 Subject: GENERIC kernel issues Date: Sun, 3 Mar 2013 11:43:21 -0800 Message-Id: To: freebsd-arm@freebsd.org Mime-Version: 1.0 (Apple Message framework v1283) X-Mailer: Apple Mail (2.1283) X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 03 Mar 2013 19:43:31 -0000 --Apple-Mail=_F90B5CAF-B0AA-4609-AF80-4A91CA3659E3 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii I spent some time yesterday putting together a kernel configuration for a GENERIC ARM kernel that would support both RaspberryPi and BeagleBone. Just to see how far I could get. Here's a list of the problems I've found so far: ** Multiple MMU support. If you put these two lines into an ARM kernel config, the build will fail in the MMU code: cpu CPU_ARM1176 cpu CPU_CORTEXA Basically, this turns on the support for multiple MMUs but the ARMv6/ARMv7 MMU definitions don't play nicely with run-time MMU selection. ** PHYSADDR/KERNPHYSADDR hardwiring. Ian has made a lot of progress and I'm working on some related changes to address this. I think we understand how to eliminate these constants and replace them with run-time detection of the load address. I'm still not sure what changes might be needed to the loader to make this work. ** PIPT vs. VIVT cache management. This is currently set at compile time; we'll need to have a way to set this at run time based on the CPU. (I have some skeletal code to select CPU at the top of initarm by inspecting the FDT. I presume this switch will be routine once a robust version of that is in place.) ** TI processor detection. This is currently hardwired at build time, so we cannot currently build a kernel that supports both AM335x and OMAP4, for example. Question: should we create a /projects/arm-generic/ branch to hold this work while it's in flux? Tim --Apple-Mail=_F90B5CAF-B0AA-4609-AF80-4A91CA3659E3 Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP using GPGMail -----BEGIN PGP SIGNATURE----- Version: GnuPG/MacGPG2 v2.0.18 (Darwin) iQEcBAEBAgAGBQJRM6faAAoJEGMNyGo0rfFBdfAH/R7xOKp9xQ2zz8FSKT7M6lan VOf6ArQqMpfNkaUyr4lmAN5NNAkXWLmc4H78RrL6aWQHTEqH+xAFaQTnthZzCTOF bRC3olzQGCbhP7IBn51Z9waYa8Q/PRKdBbApEPaL2mOzX0XHvipIXn3GAZgxVCv7 YZnuiPfCAkWOiZMWBpLdKK2Jo9DZBPKSfKzxHqYLUbG0H2FyJmgUsHi35MQJiDKq VWe8KQ9jEneu+HO5V3xEsS1Yd1m873w7e0TjhIteWH1MqnDQd1MGcF1oO+u+naAa WjvBcEcuuTQaAi07Ii8H4iJn3pATg+Q6q5RX8MOSsj7Ih3mjBwRnE37GV26X8Us= =zsr9 -----END PGP SIGNATURE----- --Apple-Mail=_F90B5CAF-B0AA-4609-AF80-4A91CA3659E3--