From owner-svn-src-head@freebsd.org Thu Sep 7 21:31:09 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 438F7E11251; Thu, 7 Sep 2017 21:31:09 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id C9F9676C8A; Thu, 7 Sep 2017 21:31:08 +0000 (UTC) (envelope-from cem@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v87LV7kg052599; Thu, 7 Sep 2017 21:31:07 GMT (envelope-from cem@FreeBSD.org) Received: (from cem@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v87LV7cn052597; Thu, 7 Sep 2017 21:31:07 GMT (envelope-from cem@FreeBSD.org) Message-Id: <201709072131.v87LV7cn052597@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: cem set sender to cem@FreeBSD.org using -f From: Conrad Meyer Date: Thu, 7 Sep 2017 21:31:07 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r323288 - in head/sys/x86: include x86 X-SVN-Group: head X-SVN-Commit-Author: cem X-SVN-Commit-Paths: in head/sys/x86: include x86 X-SVN-Commit-Revision: 323288 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Sep 2017 21:31:09 -0000 Author: cem Date: Thu Sep 7 21:31:07 2017 New Revision: 323288 URL: https://svnweb.freebsd.org/changeset/base/323288 Log: x86 MCA: Enable AMD thresholding support on 17h 17h supports MCA thresholding in the same way as 16h and earlier. Supposedly a ScalableMca feature bit in CPUID 8000_0007:EBX must be set, but that was not true for earlier models, so be careful about relying on it. While here, document a missing bit in LS MCA MISC0. Reviewed by: truckman Sponsored by: Dell EMC Isilon Differential Revision: https://reviews.freebsd.org/D12237 Modified: head/sys/x86/include/specialreg.h head/sys/x86/x86/mca.c Modified: head/sys/x86/include/specialreg.h ============================================================================== --- head/sys/x86/include/specialreg.h Thu Sep 7 21:29:51 2017 (r323287) +++ head/sys/x86/include/specialreg.h Thu Sep 7 21:31:07 2017 (r323288) @@ -718,6 +718,7 @@ #define MC_MISC_AMDNB_VAL 0x8000000000000000 /* Counter presence valid */ #define MC_MISC_AMDNB_CNTP 0x4000000000000000 /* Counter present */ #define MC_MISC_AMDNB_LOCK 0x2000000000000000 /* Register locked */ +#define MC_MISC_AMDNB_INTP 0x1000000000000000 /* Int. type can generate interrupts */ #define MC_MISC_AMDNB_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */ #define MC_MISC_AMDNB_LVT_SHIFT 52 #define MC_MISC_AMDNB_CNTEN 0x0008000000000000 /* Counter enabled */ Modified: head/sys/x86/x86/mca.c ============================================================================== --- head/sys/x86/x86/mca.c Thu Sep 7 21:29:51 2017 (r323287) +++ head/sys/x86/x86/mca.c Thu Sep 7 21:31:07 2017 (r323288) @@ -132,8 +132,20 @@ static int amd_elvt = -1; static inline bool amd_thresholding_supported(void) { - return (cpu_vendor_id == CPU_VENDOR_AMD && - CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16); + if (cpu_vendor_id != CPU_VENDOR_AMD) + return (false); + /* + * The RASCap register is wholly reserved in families 0x10-0x15 (through model 1F). + * + * It begins to be documented in family 0x15 model 30 and family 0x16, + * but neither of these families documents the ScalableMca bit, which + * supposedly defines the presence of this feature on family 0x17. + */ + if (CPUID_TO_FAMILY(cpu_id) >= 0x10 && CPUID_TO_FAMILY(cpu_id) <= 0x16) + return (true); + if (CPUID_TO_FAMILY(cpu_id) >= 0x17) + return ((amd_rascap & AMDRAS_SCALABLE_MCA) != 0); + return (false); } #endif