From owner-svn-src-head@FreeBSD.ORG Thu Aug 19 02:04:35 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 87A101065697; Thu, 19 Aug 2010 02:04:35 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 5CCBB8FC15; Thu, 19 Aug 2010 02:04:35 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o7J24ZQF086408; Thu, 19 Aug 2010 02:04:35 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o7J24ZLI086406; Thu, 19 Aug 2010 02:04:35 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201008190204.o7J24ZLI086406@svn.freebsd.org> From: Adrian Chadd Date: Thu, 19 Aug 2010 02:04:35 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r211477 - head/sys/mips/atheros X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Aug 2010 02:04:35 -0000 Author: adrian Date: Thu Aug 19 02:04:35 2010 New Revision: 211477 URL: http://svn.freebsd.org/changeset/base/211477 Log: Make if_arge use the new cpuops rather than hard coding the DDR flush registers. Modified: head/sys/mips/atheros/if_arge.c Modified: head/sys/mips/atheros/if_arge.c ============================================================================== --- head/sys/mips/atheros/if_arge.c Thu Aug 19 02:03:12 2010 (r211476) +++ head/sys/mips/atheros/if_arge.c Thu Aug 19 02:04:35 2010 (r211477) @@ -79,6 +79,7 @@ MODULE_DEPEND(arge, miibus, 1, 1, 1); #include #include +#include #undef ARGE_DEBUG #ifdef ARGE_DEBUG @@ -181,14 +182,11 @@ MTX_SYSINIT(miibus_mtx, &miibus_mtx, "ar static void arge_flush_ddr(struct arge_softc *sc) { - - ATH_WRITE_REG(sc->arge_ddr_flush_reg, 1); - while (ATH_READ_REG(sc->arge_ddr_flush_reg) & 1) - ; - - ATH_WRITE_REG(sc->arge_ddr_flush_reg, 1); - while (ATH_READ_REG(sc->arge_ddr_flush_reg) & 1) - ; + if (sc->arge_mac_unit == 0) { + ar71xx_device_flush_ddr_ge0(); + } else { + ar71xx_device_flush_ddr_ge1(); + } } static int @@ -237,11 +235,9 @@ arge_attach(device_t dev) KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), ("if_arge: Only MAC0 and MAC1 supported")); if (sc->arge_mac_unit == 0) { - sc->arge_ddr_flush_reg = AR71XX_WB_FLUSH_GE0; sc->arge_pll_reg = AR71XX_PLL_ETH_INT0_CLK; sc->arge_pll_reg_shift = 17; } else { - sc->arge_ddr_flush_reg = AR71XX_WB_FLUSH_GE1; sc->arge_pll_reg = AR71XX_PLL_ETH_INT1_CLK; sc->arge_pll_reg_shift = 19; } @@ -381,19 +377,9 @@ arge_attach(device_t dev) DELAY(20); /* Step 2. Punt the MAC core from the central reset register */ - reg = ATH_READ_REG(AR71XX_RST_RESET); - if (sc->arge_mac_unit == 0) - reg |= RST_RESET_GE0_MAC; - else if (sc->arge_mac_unit == 1) - reg |= RST_RESET_GE1_MAC; - ATH_WRITE_REG(AR71XX_RST_RESET, reg); + ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); DELAY(100); - reg = ATH_READ_REG(AR71XX_RST_RESET); - if (sc->arge_mac_unit == 0) - reg &= ~RST_RESET_GE0_MAC; - else if (sc->arge_mac_unit == 1) - reg &= ~RST_RESET_GE1_MAC; - ATH_WRITE_REG(AR71XX_RST_RESET, reg); + ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC); /* Step 3. Reconfigure MAC block */ ARGE_WRITE(sc, AR71XX_MAC_CFG1,