From owner-svn-src-head@freebsd.org Thu Apr 13 11:56:28 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 93DD4D3BD69; Thu, 13 Apr 2017 11:56:28 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 4AA82B24; Thu, 13 Apr 2017 11:56:28 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v3DBuRdT008715; Thu, 13 Apr 2017 11:56:27 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v3DBuRKI008713; Thu, 13 Apr 2017 11:56:27 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201704131156.v3DBuRKI008713@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Thu, 13 Apr 2017 11:56:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r316755 - in head/sys/arm64: arm64 include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 13 Apr 2017 11:56:28 -0000 Author: andrew Date: Thu Apr 13 11:56:27 2017 New Revision: 316755 URL: https://svnweb.freebsd.org/changeset/base/316755 Log: Add SCTLR bits added in ARMv8.1 and ARMv8.2 and start to use them in the early boot code. Sponsored by: DARPA, AFRL Modified: head/sys/arm64/arm64/locore.S head/sys/arm64/include/armreg.h Modified: head/sys/arm64/arm64/locore.S ============================================================================== --- head/sys/arm64/arm64/locore.S Thu Apr 13 09:59:12 2017 (r316754) +++ head/sys/arm64/arm64/locore.S Thu Apr 13 11:56:27 2017 (r316755) @@ -626,12 +626,13 @@ tcr: TCR_CACHE_ATTRS | TCR_SMP_ATTRS) sctlr_set: /* Bits to set */ - .quad (SCTLR_UCI | SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ + .quad (SCTLR_LSMAOE | SCTLR_nTLSMD | SCTLR_UCI | SCTLR_SPAN | \ + SCTLR_nTWE | SCTLR_nTWI | SCTLR_UCT | SCTLR_DZE | \ SCTLR_I | SCTLR_SED | SCTLR_SA0 | SCTLR_SA | SCTLR_C | SCTLR_M) sctlr_clear: /* Bits to clear */ - .quad (SCTLR_EE | SCTLR_EOE | SCTLR_WXN | SCTLR_UMA | SCTLR_ITD | \ - SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A) + .quad (SCTLR_EE | SCTLR_EOE | SCTLR_IESB | SCTLR_WXN | SCTLR_UMA | \ + SCTLR_ITD | SCTLR_THEE | SCTLR_CP15BEN | SCTLR_A) .globl abort abort: Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Thu Apr 13 09:59:12 2017 (r316754) +++ head/sys/arm64/include/armreg.h Thu Apr 13 11:56:27 2017 (r316755) @@ -384,8 +384,8 @@ #define PAR_S_MASK (0x1 << PAR_S_SHIFT) /* SCTLR_EL1 - System Control Register */ -#define SCTLR_RES0 0xc8222400 /* Reserved, write 0 */ -#define SCTLR_RES1 0x30d00800 /* Reserved, write 1 */ +#define SCTLR_RES0 0xc8222400 /* Reserved ARMv8.0, write 0 */ +#define SCTLR_RES1 0x30d00800 /* Reserved ARMv8.0, write 1 */ #define SCTLR_M 0x00000001 #define SCTLR_A 0x00000002 @@ -403,9 +403,13 @@ #define SCTLR_nTWI 0x00010000 #define SCTLR_nTWE 0x00040000 #define SCTLR_WXN 0x00080000 +#define SCTLR_IESB 0x00200000 +#define SCTLR_SPAN 0x00800000 #define SCTLR_EOE 0x01000000 #define SCTLR_EE 0x02000000 #define SCTLR_UCI 0x04000000 +#define SCTLR_nTLSMD 0x10000000 +#define SCTLR_LSMAOE 0x20000000 /* SPSR_EL1 */ /*