From owner-freebsd-hackers@FreeBSD.ORG Sat Mar 28 19:50:01 2015 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id BAFEEAB4; Sat, 28 Mar 2015 19:50:01 +0000 (UTC) Received: from zxy.spb.ru (zxy.spb.ru [195.70.199.98]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 6DD25E93; Sat, 28 Mar 2015 19:50:01 +0000 (UTC) Received: from slw by zxy.spb.ru with local (Exim 4.84 (FreeBSD)) (envelope-from ) id 1Ybwk3-0000Zy-DI; Sat, 28 Mar 2015 22:49:59 +0300 Date: Sat, 28 Mar 2015 22:49:59 +0300 From: Slawa Olhovchenkov To: Adrian Chadd Subject: Re: irq cpu binding Message-ID: <20150328194959.GE23643@zxy.spb.ru> References: <20150328112035.GZ23643@zxy.spb.ru> <20150328154031.GA23643@zxy.spb.ru> <20150328181026.GB23643@zxy.spb.ru> <20150328183147.GC23643@zxy.spb.ru> <20150328192505.GD23643@zxy.spb.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: slw@zxy.spb.ru X-SA-Exim-Scanned: No (on zxy.spb.ru); SAEximRunCond expanded to false Cc: "freebsd-hackers@freebsd.org" X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Mar 2015 19:50:01 -0000 On Sat, Mar 28, 2015 at 12:33:52PM -0700, Adrian Chadd wrote: > That's done deferred by the bus interrupt wiring. That's something > John's been looking into as part of the general NUMA work (and I'm > trying to debug right now, on dual-socket boxes with ixgbe. :-) > > Look at bus_bind_intr() and the twisty path to intr_event_bind(), then > x86/x86/intr_machdep.c:intr_assign_cpu(), then intr_shuffle_cpus() at > boot, versus what happens via calls to pic_assign_cpu to setup the > wiring. This is very complex to me -- I am not familar with current x86 hardware. Hmm. I see intr_setaffinity and intr_bind. And I don't see using this nor ixgbe nor cxgbe. Anyway, I am re-set CPUs compared to initial assigned in ixgbe/cxgbe drivers.