Date: Tue, 9 Jun 2020 15:56:41 +0000 (UTC) From: Ruslan Bukin <br@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r361968 - in head/sys: arm64/coresight conf Message-ID: <202006091556.059FufZl076630@repo.freebsd.org>
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Author: br Date: Tue Jun 9 15:56:41 2020 New Revision: 361968 URL: https://svnweb.freebsd.org/changeset/base/361968 Log: Rename coresight drivers: use underscores in filenames. Sponsored by: DARPA, AFRL Added: head/sys/arm64/coresight/coresight_cmd.c - copied unchanged from r361967, head/sys/arm64/coresight/coresight-cmd.c head/sys/arm64/coresight/coresight_cpu_debug.c - copied unchanged from r361967, head/sys/arm64/coresight/coresight-cpu-debug.c head/sys/arm64/coresight/coresight_dynamic_replicator.c - copied unchanged from r361967, head/sys/arm64/coresight/coresight-dynamic-replicator.c head/sys/arm64/coresight/coresight_etm4x.c - copied, changed from r361967, head/sys/arm64/coresight/coresight-etm4x.c head/sys/arm64/coresight/coresight_etm4x.h - copied unchanged from r361967, head/sys/arm64/coresight/coresight-etm4x.h head/sys/arm64/coresight/coresight_funnel.c - copied, changed from r361967, head/sys/arm64/coresight/coresight-funnel.c head/sys/arm64/coresight/coresight_funnel.h - copied unchanged from r361967, head/sys/arm64/coresight/coresight-funnel.h head/sys/arm64/coresight/coresight_tmc.c - copied, changed from r361967, head/sys/arm64/coresight/coresight-tmc.c head/sys/arm64/coresight/coresight_tmc.h - copied unchanged from r361967, head/sys/arm64/coresight/coresight-tmc.h Deleted: head/sys/arm64/coresight/coresight-cmd.c head/sys/arm64/coresight/coresight-cpu-debug.c head/sys/arm64/coresight/coresight-dynamic-replicator.c head/sys/arm64/coresight/coresight-etm4x.c head/sys/arm64/coresight/coresight-etm4x.h head/sys/arm64/coresight/coresight-funnel.c head/sys/arm64/coresight/coresight-funnel.h head/sys/arm64/coresight/coresight-tmc.c head/sys/arm64/coresight/coresight-tmc.h Modified: head/sys/conf/files.arm64 Copied: head/sys/arm64/coresight/coresight_cmd.c (from r361967, head/sys/arm64/coresight/coresight-cmd.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_cmd.c Tue Jun 9 15:56:41 2020 (r361968, copy of r361967, head/sys/arm64/coresight/coresight-cmd.c) @@ -0,0 +1,156 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <arm64/coresight/coresight.h> + +#include "coresight_if.h" + +extern struct coresight_device_list cs_devs; + +static struct coresight_device * +coresight_next_device(struct coresight_device *cs_dev, + struct coresight_event *event) +{ + struct coresight_device *out; + struct endpoint *out_endp; + struct endpoint *endp; + + TAILQ_FOREACH(endp, &cs_dev->pdata->endpoints, link) { + if (endp->slave != 0) + continue; + + out = coresight_get_output_device(endp, &out_endp); + if (out != NULL) { + if (LIST_EMPTY(&event->endplist)) { + /* Add source device */ + endp->cs_dev = cs_dev; + LIST_INSERT_HEAD(&event->endplist, endp, + endplink); + } + + /* Add output device */ + out_endp->cs_dev = out; + LIST_INSERT_HEAD(&event->endplist, out_endp, endplink); + + return (out); + } + } + + return (NULL); +} + +static int +coresight_build_list(struct coresight_device *cs_dev, + struct coresight_event *event) +{ + struct coresight_device *out; + + out = cs_dev; + while (out != NULL) + out = coresight_next_device(out, event); + + return (0); +} + +int +coresight_init_event(int cpu, struct coresight_event *event) +{ + struct coresight_device *cs_dev; + struct endpoint *endp; + + /* Start building path from source device */ + TAILQ_FOREACH(cs_dev, &cs_devs, link) { + if (cs_dev->dev_type == event->src && + cs_dev->pdata->cpu == cpu) { + LIST_INIT(&event->endplist); + coresight_build_list(cs_dev, event); + break; + } + } + + /* Ensure Coresight is initialized for the CPU */ + TAILQ_FOREACH(cs_dev, &cs_devs, link) { + if (cs_dev->dev_type == CORESIGHT_CPU_DEBUG && + cs_dev->pdata->cpu == cpu) + CORESIGHT_INIT(cs_dev->dev); + } + + /* Init all devices in the path */ + LIST_FOREACH(endp, &event->endplist, endplink) { + cs_dev = endp->cs_dev; + CORESIGHT_INIT(cs_dev->dev); + } + + return (0); +} + +void +coresight_enable(int cpu, struct coresight_event *event) +{ + struct coresight_device *cs_dev; + struct endpoint *endp; + + LIST_FOREACH(endp, &event->endplist, endplink) { + cs_dev = endp->cs_dev; + CORESIGHT_ENABLE(cs_dev->dev, endp, event); + } +} + +void +coresight_disable(int cpu, struct coresight_event *event) +{ + struct coresight_device *cs_dev; + struct endpoint *endp; + + LIST_FOREACH(endp, &event->endplist, endplink) { + cs_dev = endp->cs_dev; + CORESIGHT_DISABLE(cs_dev->dev, endp, event); + } +} + +void +coresight_read(int cpu, struct coresight_event *event) +{ + struct endpoint *endp; + + LIST_FOREACH(endp, &event->endplist, endplink) + CORESIGHT_READ(endp->cs_dev->dev, endp, event); +} Copied: head/sys/arm64/coresight/coresight_cpu_debug.c (from r361967, head/sys/arm64/coresight/coresight-cpu-debug.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_cpu_debug.c Tue Jun 9 15:56:41 2020 (r361968, copy of r361967, head/sys/arm64/coresight/coresight-cpu-debug.c) @@ -0,0 +1,164 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by BAE Systems, the University of Cambridge + * Computer Laboratory, and Memorial University under DARPA/AFRL contract + * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing + * (TC) research program. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <arm64/coresight/coresight.h> + +#include "coresight_if.h" + +#define EDPCSR 0x0a0 +#define EDCIDSR 0x0a4 +#define EDVIDSR 0x0a8 +#define EDPCSR_HI 0x0ac +#define EDOSLAR 0x300 +#define EDPRCR 0x310 +#define EDPRCR_COREPURQ (1 << 3) +#define EDPRCR_CORENPDRQ (1 << 0) +#define EDPRSR 0x314 +#define EDDEVID1 0xfc4 +#define EDDEVID 0xfc8 + +static struct ofw_compat_data compat_data[] = { + { "arm,coresight-cpu-debug", 1 }, + { NULL, 0 } +}; + +struct debug_softc { + struct resource *res; + struct coresight_platform_data *pdata; +}; + +static struct resource_spec debug_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static int +debug_init(device_t dev) +{ + struct debug_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + + /* Unlock Coresight */ + bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK); + + /* Unlock Debug */ + bus_write_4(sc->res, EDOSLAR, 0); + + /* Already initialized? */ + reg = bus_read_4(sc->res, EDPRCR); + if (reg & EDPRCR_CORENPDRQ) + return (0); + + /* Enable power */ + reg |= EDPRCR_COREPURQ; + bus_write_4(sc->res, EDPRCR, reg); + + do { + reg = bus_read_4(sc->res, EDPRSR); + } while ((reg & EDPRCR_CORENPDRQ) == 0); + + return (0); +} + +static int +debug_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Coresight CPU Debug"); + + return (BUS_PROBE_DEFAULT); +} + +static int +debug_attach(device_t dev) +{ + struct coresight_desc desc; + struct debug_softc *sc; + + sc = device_get_softc(dev); + + if (bus_alloc_resources(dev, debug_spec, &sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + return (ENXIO); + } + + sc->pdata = coresight_get_platform_data(dev); + desc.pdata = sc->pdata; + desc.dev = dev; + desc.dev_type = CORESIGHT_CPU_DEBUG; + coresight_register(&desc); + + return (0); +} + +static device_method_t debug_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, debug_probe), + DEVMETHOD(device_attach, debug_attach), + + /* Coresight interface */ + DEVMETHOD(coresight_init, debug_init), + DEVMETHOD_END +}; + +static driver_t debug_driver = { + "debug", + debug_methods, + sizeof(struct debug_softc), +}; + +static devclass_t debug_devclass; + +EARLY_DRIVER_MODULE(debug, simplebus, debug_driver, debug_devclass, + 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LATE); +MODULE_VERSION(debug, 1); Copied: head/sys/arm64/coresight/coresight_dynamic_replicator.c (from r361967, head/sys/arm64/coresight/coresight-dynamic-replicator.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_dynamic_replicator.c Tue Jun 9 15:56:41 2020 (r361968, copy of r361967, head/sys/arm64/coresight/coresight-dynamic-replicator.c) @@ -0,0 +1,172 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by BAE Systems, the University of Cambridge + * Computer Laboratory, and Memorial University under DARPA/AFRL contract + * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing + * (TC) research program. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/rman.h> +#include <sys/kernel.h> +#include <sys/module.h> +#include <machine/bus.h> + +#include <arm64/coresight/coresight.h> + +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include "coresight_if.h" + +#define REPLICATOR_IDFILTER0 0x00 +#define REPLICATOR_IDFILTER1 0x04 + +static struct ofw_compat_data compat_data[] = { + { "arm,coresight-dynamic-replicator", 1 }, + { NULL, 0 } +}; + +struct replicator_softc { + struct resource *res; + struct coresight_platform_data *pdata; +}; + +static struct resource_spec replicator_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +static int +replicator_init(device_t dev) +{ + struct replicator_softc *sc; + + sc = device_get_softc(dev); + + /* Unlock Coresight */ + bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK); + + return (0); +} + +static int +replicator_enable(device_t dev, struct endpoint *endp, + struct coresight_event *event) +{ + struct replicator_softc *sc; + + sc = device_get_softc(dev); + + /* Enable the port. Keep the other port disabled */ + if (endp->reg == 0) { + bus_write_4(sc->res, REPLICATOR_IDFILTER0, 0x00); + bus_write_4(sc->res, REPLICATOR_IDFILTER1, 0xff); + } else { + bus_write_4(sc->res, REPLICATOR_IDFILTER0, 0xff); + bus_write_4(sc->res, REPLICATOR_IDFILTER1, 0x00); + } + + return (0); +} + +static void +replicator_disable(device_t dev, struct endpoint *endp, + struct coresight_event *event) +{ + struct replicator_softc *sc; + + sc = device_get_softc(dev); + + bus_write_4(sc->res, REPLICATOR_IDFILTER0, 0xff); + bus_write_4(sc->res, REPLICATOR_IDFILTER1, 0xff); +} + +static int +replicator_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Coresight Dynamic Replicator"); + + return (BUS_PROBE_DEFAULT); +} + +static int +replicator_attach(device_t dev) +{ + struct replicator_softc *sc; + struct coresight_desc desc; + + sc = device_get_softc(dev); + + if (bus_alloc_resources(dev, replicator_spec, &sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + return (ENXIO); + } + + sc->pdata = coresight_get_platform_data(dev); + desc.pdata = sc->pdata; + desc.dev = dev; + desc.dev_type = CORESIGHT_DYNAMIC_REPLICATOR; + coresight_register(&desc); + + return (0); +} + +static device_method_t replicator_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, replicator_probe), + DEVMETHOD(device_attach, replicator_attach), + + /* Coresight interface */ + DEVMETHOD(coresight_init, replicator_init), + DEVMETHOD(coresight_enable, replicator_enable), + DEVMETHOD(coresight_disable, replicator_disable), + DEVMETHOD_END +}; + +static driver_t replicator_driver = { + "replicator", + replicator_methods, + sizeof(struct replicator_softc), +}; + +static devclass_t replicator_devclass; + +DRIVER_MODULE(replicator, simplebus, replicator_driver, replicator_devclass, + 0, 0); +MODULE_VERSION(replicator, 1); Copied and modified: head/sys/arm64/coresight/coresight_etm4x.c (from r361967, head/sys/arm64/coresight/coresight-etm4x.c) ============================================================================== --- head/sys/arm64/coresight/coresight-etm4x.c Tue Jun 9 15:17:23 2020 (r361967, copy source) +++ head/sys/arm64/coresight/coresight_etm4x.c Tue Jun 9 15:56:41 2020 (r361968) @@ -44,7 +44,7 @@ __FBSDID("$FreeBSD$"); #include <dev/ofw/ofw_bus_subr.h> #include <arm64/coresight/coresight.h> -#include <arm64/coresight/coresight-etm4x.h> +#include <arm64/coresight/coresight_etm4x.h> #include "coresight_if.h" Copied: head/sys/arm64/coresight/coresight_etm4x.h (from r361967, head/sys/arm64/coresight/coresight-etm4x.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_etm4x.h Tue Jun 9 15:56:41 2020 (r361968, copy of r361967, head/sys/arm64/coresight/coresight-etm4x.h) @@ -0,0 +1,175 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by BAE Systems, the University of Cambridge + * Computer Laboratory, and Memorial University under DARPA/AFRL contract + * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing + * (TC) research program. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _ARM64_CORESIGHT_ETM4X_H_ +#define _ARM64_CORESIGHT_ETM4X_H_ + +#define TRCPRGCTLR 0x004 /* Trace Programming Control Register */ +#define TRCPRGCTLR_EN (1 << 0) /* Trace unit enable bit */ +#define TRCPROCSELR 0x008 /* Trace PE Select Control Register */ +#define TRCSTATR 0x00C /* Trace Trace Status Register */ +#define TRCSTATR_PMSTABLE (1 << 1) /* The programmers' model is stable. */ +#define TRCSTATR_IDLE (1 << 0) /* The trace unit is idle. */ +#define TRCCONFIGR 0x010 /* Trace Trace Configuration Register */ +#define TRCCONFIGR_DV (1 << 17) /* Data value tracing is enabled when INSTP0 is not 0b00 */ +#define TRCCONFIGR_DA (1 << 16) /* Data address tracing is enabled when INSTP0 is not 0b00. */ +#define TRCCONFIGR_VMIDOPT (1 << 15) /* Control bit to configure the Virtual context identifier value */ +#define TRCCONFIGR_QE_S 13 /* Q element enable field */ +#define TRCCONFIGR_QE_M (0x3 << TRCCONFIGR_QE_S) +#define TRCCONFIGR_RS (1 << 12) /* Return stack enable bit */ +#define TRCCONFIGR_TS (1 << 11) /* Global timestamp tracing is enabled. */ +#define TRCCONFIGR_COND_S 8 /* Conditional instruction tracing bit. */ +#define TRCCONFIGR_COND_M (0x7 << TRCCONFIGR_COND_S) +#define TRCCONFIGR_COND_DIS 0 +#define TRCCONFIGR_COND_LDR (1 << TRCCONFIGR_COND_S) /* Conditional load instructions are traced. */ +#define TRCCONFIGR_COND_STR (2 << TRCCONFIGR_COND_S) /* Conditional store instructions are traced. */ +#define TRCCONFIGR_COND_LDRSTR (3 << TRCCONFIGR_COND_S) /* Conditional load and store instructions are traced. */ +#define TRCCONFIGR_COND_ALL (7 << TRCCONFIGR_COND_S) /* All conditional instructions are traced. */ +#define TRCCONFIGR_VMID (1 << 7) /* Virtual context identifier tracing is enabled. */ +#define TRCCONFIGR_CID (1 << 6) /* Context ID tracing is enabled. */ +#define TRCCONFIGR_CCI (1 << 4) /* Cycle counting in the instruction trace is enabled. */ +#define TRCCONFIGR_BB (1 << 3) /* Branch broadcast mode is enabled. */ +#define TRCCONFIGR_INSTP0_S 1 /* Instruction P0 field. */ +#define TRCCONFIGR_INSTP0_M (0x3 << TRCCONFIGR_INSTP0_S) +#define TRCCONFIGR_INSTP0_NONE 0 /* Do not trace load and store instructions as P0 instructions. */ +#define TRCCONFIGR_INSTP0_LDR (1 << TRCCONFIGR_INSTP0_S) /* Trace load instructions as P0 instructions. */ +#define TRCCONFIGR_INSTP0_STR (2 << TRCCONFIGR_INSTP0_S) /* Trace store instructions as P0 instructions. */ +#define TRCCONFIGR_INSTP0_LDRSTR (3 << TRCCONFIGR_INSTP0_S) /* Trace load and store instructions as P0 instr. */ +#define TRCAUXCTLR 0x018 /* Trace Auxiliary Control Register */ +#define TRCEVENTCTL0R 0x020 /* Trace Event Control 0 Register */ +#define TRCEVENTCTL1R 0x024 /* Trace Event Control 1 Register */ +#define TRCSTALLCTLR 0x02C /* Trace Stall Control Register */ +#define TRCTSCTLR 0x030 /* Trace Global Timestamp Control Register */ +#define TRCSYNCPR 0x034 /* Trace Synchronization Period Register */ +#define TRCSYNCPR_PERIOD_S 0 +#define TRCSYNCPR_PERIOD_M 0x1f +#define TRCSYNCPR_1K (10 << TRCSYNCPR_PERIOD_S) +#define TRCSYNCPR_2K (11 << TRCSYNCPR_PERIOD_S) +#define TRCSYNCPR_4K (12 << TRCSYNCPR_PERIOD_S) +#define TRCCCCTLR 0x038 /* Trace Cycle Count Control Register */ +#define TRCBBCTLR 0x03C /* Trace Branch Broadcast Control Register */ +#define TRCTRACEIDR 0x040 /* Trace Trace ID Register */ +#define TRCQCTLR 0x044 /* Trace Q Element Control Register */ +#define TRCQCTLR_MODE_INC (1 << 8) /* Include mode. */ +#define TRCVICTLR 0x080 /* Trace ViewInst Main Control Register */ +#define TRCVICTLR_SSSTATUS (1 << 9) /* The start/stop logic is in the started state. */ +#define TRCVICTLR_EXLEVEL_NS_S 20 +#define TRCVICTLR_EXLEVEL_NS_M (0xf << TRCVICTLR_EXLEVEL_NS_S) +#define TRCVICTLR_EXLEVEL_NS(n) (0x1 << ((n) + TRCVICTLR_EXLEVEL_NS_S)) +#define TRCVICTLR_EXLEVEL_S_S 16 +#define TRCVICTLR_EXLEVEL_S_M (0xf << TRCVICTLR_EXLEVEL_S_S) +#define TRCVICTLR_EXLEVEL_S(n) (0x1 << ((n) + TRCVICTLR_EXLEVEL_S_S)) +#define EVENT_SEL_S 0 +#define EVENT_SEL_M (0x1f << EVENT_SEL_S) +#define TRCVIIECTLR 0x084 /* Trace ViewInst Include/Exclude Control Register */ +#define TRCVIIECTLR_INCLUDE_S 0 +#define TRCVISSCTLR 0x088 /* Trace ViewInst Start/Stop Control Register */ +#define TRCVIPCSSCTLR 0x08C /* Trace ViewInst Start/Stop PE Comparator Control Register */ +#define TRCVDCTLR 0x0A0 /* Trace ViewData Main Control Register */ +#define TRCVDCTLR_TRCEXDATA (1 << 12) /* Exception and exception return data transfers are traced */ +#define TRCVDCTLR_TBI (1 << 11) /* The trace unit assigns bits[63:56] to have the same value as bits[63:56] of the data address. */ +#define TRCVDCTLR_PCREL (1 << 10) /* The trace unit does not trace the address or value portions of PC-relative transfers. */ +#define TRCVDCTLR_SPREL_S 8 +#define TRCVDCTLR_SPREL_M (0x3 << TRCVDCTLR_SPREL_S) +#define TRCVDCTLR_EVENT_S 0 +#define TRCVDCTLR_EVENT_M (0xff << TRCVDCTLR_EVENT_S) +#define TRCVDSACCTLR 0x0A4 /* Trace ViewData Include/Exclude Single Address Comparator Control Register */ +#define TRCVDARCCTLR 0x0A8 /* Trace ViewData Include/Exclude Address Range Comparator Control Register */ +#define TRCSEQEVR(n) (0x100 + (n) * 0x4) /* Trace Sequencer State Transition Control Register [n=0-2] */ +#define TRCSEQRSTEVR 0x118 /* Trace Sequencer Reset Control Register */ +#define TRCSEQSTR 0x11C /* Trace Sequencer State Register */ +#define TRCEXTINSELR 0x120 /* Trace External Input Select Register */ +#define TRCCNTRLDVR(n) (0x140 + (n) * 0x4) /* 32 Trace Counter Reload Value Register [n=0-3] */ +#define TRCCNTCTLR(n) (0x150 + (n) * 0x4) /* 32 Trace Counter Control Register [n=0-3] */ +#define TRCCNTVR(n) (0x160 + (n) * 0x4) /* 32 Trace Counter Value Register [n=0-3] */ +#define TRCIMSPEC(n) (0x1C0 + (n) * 0x4) /* Trace IMPLEMENTATION DEFINED register [n=0-7] */ + +#define TRCIDR0(n) (0x1E0 + 0x4 * (n)) +#define TRCIDR8(n) (0x180 + 0x4 * (n)) +#define TRCIDR(n) ((n > 7) ? TRCIDR8(n) : TRCIDR0(n)) +#define TRCIDR1_TRCARCHMAJ_S 8 +#define TRCIDR1_TRCARCHMAJ_M (0xf << TRCIDR1_TRCARCHMAJ_S) +#define TRCIDR1_TRCARCHMIN_S 4 +#define TRCIDR1_TRCARCHMIN_M (0xf << TRCIDR1_TRCARCHMIN_S) + +#define TRCRSCTLR(n) (0x200 + (n) * 0x4) /* Trace Resource Selection Control Register [n=2-31] */ +#define TRCSSCCR(n) (0x280 + (n) * 0x4) /* Trace Single-shot Comparator Control Register [n=0-7] */ +#define TRCSSCSR(n) (0x2A0 + (n) * 0x4) /* Trace Single-shot Comparator Status Register [n=0-7] */ +#define TRCSSPCICR(n) (0x2C0 + (n) * 0x4) /* Trace Single-shot PE Comparator Input Control [n=0-7] */ +#define TRCOSLAR 0x300 /* Management OS Lock Access Register */ +#define TRCOSLSR 0x304 /* Management OS Lock Status Register */ +#define TRCPDCR 0x310 /* Management PowerDown Control Register */ +#define TRCPDSR 0x314 /* Management PowerDown Status Register */ +#define TRCACVR(n) (0x400 + (n) * 0x8) /* Trace Address Comparator Value Register [n=0-15] */ +#define TRCACATR(n) (0x480 + (n) * 0x8) /* Trace Address Comparator Access Type Register [n=0-15] */ +#define TRCACATR_DTBM (1 << 21) +#define TRCACATR_DATARANGE (1 << 20) +#define TRCACATR_DATASIZE_S 18 +#define TRCACATR_DATASIZE_M (0x3 << TRCACATR_DATASIZE_S) +#define TRCACATR_DATASIZE_B (0x0 << TRCACATR_DATASIZE_S) +#define TRCACATR_DATASIZE_HW (0x1 << TRCACATR_DATASIZE_S) +#define TRCACATR_DATASIZE_W (0x2 << TRCACATR_DATASIZE_S) +#define TRCACATR_DATASIZE_DW (0x3 << TRCACATR_DATASIZE_S) +#define TRCACATR_DATAMATCH_S 16 +#define TRCACATR_DATAMATCH_M (0x3 << TRCACATR_DATAMATCH_S) +#define TRCACATR_EXLEVEL_S_S 8 +#define TRCACATR_EXLEVEL_S_M (0xf << TRCACATR_EXLEVEL_S_S) +#define TRCACATR_EXLEVEL_S(n) (0x1 << ((n) + TRCACATR_EXLEVEL_S_S)) +#define TRCACATR_EXLEVEL_NS_S 12 +#define TRCACATR_EXLEVEL_NS_M (0xf << TRCACATR_EXLEVEL_NS_S) +#define TRCACATR_EXLEVEL_NS(n) (0x1 << ((n) + TRCACATR_EXLEVEL_NS_S)) +#define TRCDVCVR(n) (0x500 + (n) * 0x8) /* Trace Data Value Comparator Value Register [n=0-7] */ +#define TRCDVCMR(n) (0x580 + (n) * 0x8) /* Trace Data Value Comparator Mask Register [n=0-7] */ +#define TRCCIDCVR(n) (0x600 + (n) * 0x8) /* Trace Context ID Comparator Value Register [n=0-7] */ +#define TRCVMIDCVR(n) (0x640 + (n) * 0x8) /* Trace Virtual context identifier Comparator Value [n=0-7] */ +#define TRCCIDCCTLR0 0x680 /* Trace Context ID Comparator Control Register 0 */ +#define TRCCIDCCTLR1 0x684 /* Trace Context ID Comparator Control Register 1 */ +#define TRCVMIDCCTLR0 0x688 /* Trace Virtual context identifier Comparator Control Register 0 */ +#define TRCVMIDCCTLR1 0x68C /* Trace Virtual context identifier Comparator Control Register 1 */ +#define TRCITCTRL 0xF00 /* Management Integration Mode Control register */ +#define TRCCLAIMSET 0xFA0 /* Trace Claim Tag Set register */ +#define TRCCLAIMCLR 0xFA4 /* Trace Claim Tag Clear register */ +#define TRCDEVAFF0 0xFA8 /* Management Device Affinity register 0 */ +#define TRCDEVAFF1 0xFAC /* Management Device Affinity register 1 */ +#define TRCLAR 0xFB0 /* Management Software Lock Access Register */ +#define TRCLSR 0xFB4 /* Management Software Lock Status Register */ +#define TRCAUTHSTATUS 0xFB8 /* Management Authentication Status register */ +#define TRCDEVARCH 0xFBC /* Management Device Architecture register */ +#define TRCDEVID 0xFC8 /* Management Device ID register */ +#define TRCDEVTYPE 0xFCC /* Management Device Type register */ +#define TRCPIDR4 0xFD0 /* Management Peripheral ID4 Register */ +#define TRCPIDR(n) (0xFE0 + (n) * 0x4) /* Management Peripheral IDn Register [n=0-3] */ +#define TRCPIDR567(n) (0xFD4 + ((n) - 5) * 0x4) /* Management Peripheral ID5 to Peripheral ID7 Registers */ +#define TRCCIDR(n) (0xFF0 + (n) * 0x4) /* Management Component IDn Register [n=0-4] */ + +#endif /* !_ARM64_CORESIGHT_ETM4X_H_ */ Copied and modified: head/sys/arm64/coresight/coresight_funnel.c (from r361967, head/sys/arm64/coresight/coresight-funnel.c) ============================================================================== --- head/sys/arm64/coresight/coresight-funnel.c Tue Jun 9 15:17:23 2020 (r361967, copy source) +++ head/sys/arm64/coresight/coresight_funnel.c Tue Jun 9 15:56:41 2020 (r361968) @@ -41,7 +41,7 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <arm64/coresight/coresight.h> -#include <arm64/coresight/coresight-funnel.h> +#include <arm64/coresight/coresight_funnel.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> Copied: head/sys/arm64/coresight/coresight_funnel.h (from r361967, head/sys/arm64/coresight/coresight-funnel.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_funnel.h Tue Jun 9 15:56:41 2020 (r361968, copy of r361967, head/sys/arm64/coresight/coresight-funnel.h) @@ -0,0 +1,66 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by BAE Systems, the University of Cambridge + * Computer Laboratory, and Memorial University under DARPA/AFRL contract + * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing + * (TC) research program. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _ARM64_CORESIGHT_CORESIGHT_FUNNEL_H_ +#define _ARM64_CORESIGHT_CORESIGHT_FUNNEL_H_ + +#define FUNNEL_FUNCTL 0x000 /* Funnel Control Register */ +#define FUNCTL_HOLDTIME_SHIFT 8 +#define FUNCTL_HOLDTIME_MASK (0xf << FUNCTL_HOLDTIME_SHIFT) +#define FUNNEL_PRICTL 0x004 /* Priority Control Register */ +#define FUNNEL_ITATBDATA0 0xEEC /* Integration Register, ITATBDATA0 */ +#define FUNNEL_ITATBCTR2 0xEF0 /* Integration Register, ITATBCTR2 */ +#define FUNNEL_ITATBCTR1 0xEF4 /* Integration Register, ITATBCTR1 */ +#define FUNNEL_ITATBCTR0 0xEF8 /* Integration Register, ITATBCTR0 */ +#define FUNNEL_IMCR 0xF00 /* Integration Mode Control Register */ +#define FUNNEL_CTSR 0xFA0 /* Claim Tag Set Register */ +#define FUNNEL_CTCR 0xFA4 /* Claim Tag Clear Register */ +#define FUNNEL_LOCKACCESS 0xFB0 /* Lock Access */ +#define FUNNEL_LOCKSTATUS 0xFB4 /* Lock Status */ +#define FUNNEL_AUTHSTATUS 0xFB8 /* Authentication status */ +#define FUNNEL_DEVICEID 0xFC8 /* Device ID */ +#define FUNNEL_DEVICETYPE 0xFCC /* Device Type Identifier */ +#define FUNNEL_PERIPH4 0xFD0 /* Peripheral ID4 */ +#define FUNNEL_PERIPH5 0xFD4 /* Peripheral ID5 */ +#define FUNNEL_PERIPH6 0xFD8 /* Peripheral ID6 */ +#define FUNNEL_PERIPH7 0xFDC /* Peripheral ID7 */ +#define FUNNEL_PERIPH0 0xFE0 /* Peripheral ID0 */ +#define FUNNEL_PERIPH1 0xFE4 /* Peripheral ID1 */ +#define FUNNEL_PERIPH2 0xFE8 /* Peripheral ID2 */ +#define FUNNEL_PERIPH3 0xFEC /* Peripheral ID3 */ +#define FUNNEL_COMP0 0xFF0 /* Component ID0 */ +#define FUNNEL_COMP1 0xFF4 /* Component ID1 */ +#define FUNNEL_COMP2 0xFF8 /* Component ID2 */ +#define FUNNEL_COMP3 0xFFC /* Component ID3 */ + +#endif /* !_ARM64_CORESIGHT_CORESIGHT_FUNNEL_H_ */ Copied and modified: head/sys/arm64/coresight/coresight_tmc.c (from r361967, head/sys/arm64/coresight/coresight-tmc.c) ============================================================================== --- head/sys/arm64/coresight/coresight-tmc.c Tue Jun 9 15:17:23 2020 (r361967, copy source) +++ head/sys/arm64/coresight/coresight_tmc.c Tue Jun 9 15:56:41 2020 (r361968) @@ -40,7 +40,7 @@ __FBSDID("$FreeBSD$"); #include <machine/bus.h> #include <arm64/coresight/coresight.h> -#include <arm64/coresight/coresight-tmc.h> +#include <arm64/coresight/coresight_tmc.h> #include <dev/ofw/ofw_bus.h> #include <dev/ofw/ofw_bus_subr.h> Copied: head/sys/arm64/coresight/coresight_tmc.h (from r361967, head/sys/arm64/coresight/coresight-tmc.h) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/arm64/coresight/coresight_tmc.h Tue Jun 9 15:56:41 2020 (r361968, copy of r361967, head/sys/arm64/coresight/coresight-tmc.h) @@ -0,0 +1,119 @@ +/*- + * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _ARM64_CORESIGHT_CORESIGHT_TMC_H_ +#define _ARM64_CORESIGHT_CORESIGHT_TMC_H_ + +#define TMC_RSZ 0x004 /* RAM Size Register */ +#define TMC_STS 0x00C /* Status Register */ +#define STS_MEMERR (1 << 5) +#define STS_EMPTY (1 << 4) +#define STS_FTEMPTY (1 << 3) +#define STS_TMCREADY (1 << 2) +#define STS_TRIGGERED (1 << 1) +#define STS_FULL (1 << 0) +#define TMC_RRD 0x010 /* RAM Read Data Register */ +#define TMC_RRP 0x014 /* RAM Read Pointer Register */ +#define TMC_RWP 0x018 /* RAM Write Pointer Register */ +#define TMC_TRG 0x01C /* Trigger Counter Register */ +#define TMC_CTL 0x020 /* Control Register */ +#define CTL_TRACECAPTEN (1 << 0) /* Controls trace capture. */ +#define TMC_RWD 0x024 /* RAM Write Data Register */ +#define TMC_MODE 0x028 /* Mode Register */ +#define MODE_HW_FIFO 2 +#define MODE_SW_FIFO 1 +#define MODE_CIRCULAR_BUFFER 0 +#define TMC_LBUFLEVEL 0x02C /* Latched Buffer Fill Level */ +#define TMC_CBUFLEVEL 0x030 /* Current Buffer Fill Level */ +#define TMC_BUFWM 0x034 /* Buffer Level Water Mark */ +#define TMC_RRPHI 0x038 /* RAM Read Pointer High Register */ +#define TMC_RWPHI 0x03C /* RAM Write Pointer High Register */ +#define TMC_AXICTL 0x110 /* AXI Control Register */ +#define AXICTL_WRBURSTLEN_S 8 +#define AXICTL_WRBURSTLEN_M (0xf << AXICTL_WRBURSTLEN_S) +#define AXICTL_WRBURSTLEN_16 (0xf << AXICTL_WRBURSTLEN_S) +#define AXICTL_SG_MODE (1 << 7) /* Scatter Gather Mode */ +#define AXICTL_CACHE_CTRL_BIT3 (1 << 5) +#define AXICTL_CACHE_CTRL_BIT2 (1 << 4) +#define AXICTL_CACHE_CTRL_BIT1 (1 << 3) +#define AXICTL_CACHE_CTRL_BIT0 (1 << 2) +#define AXICTL_AXCACHE_OS (0xf << 2) +#define AXICTL_PROT_CTRL_BIT1 (1 << 1) +#define AXICTL_PROT_CTRL_BIT0 (1 << 0) +#define TMC_DBALO 0x118 /* Data Buffer Address Low Register */ +#define TMC_DBAHI 0x11C /* Data Buffer Address High Register */ +#define TMC_FFSR 0x300 /* Formatter and Flush Status Register */ +#define TMC_FFCR 0x304 /* Formatter and Flush Control Register */ +#define FFCR_EN_FMT (1 << 0) +#define FFCR_EN_TI (1 << 1) +#define FFCR_FON_FLIN (1 << 4) +#define FFCR_FON_TRIG_EVT (1 << 5) +#define FFCR_FLUSH_MAN (1 << 6) +#define FFCR_TRIGON_TRIGIN (1 << 8) +#define TMC_PSCR 0x308 /* Periodic Synchronization Counter Register */ +#define TMC_ITATBMDATA0 0xED0 /* Integration Test ATB Master Data Register 0 */ +#define TMC_ITATBMCTR2 0xED4 /* Integration Test ATB Master Interface Control 2 Register */ +#define TMC_ITATBMCTR1 0xED8 /* Integration Test ATB Master Control Register 1 */ +#define TMC_ITATBMCTR0 0xEDC /* Integration Test ATB Master Interface Control 0 Register */ +#define TMC_ITMISCOP0 0xEE0 /* Integration Test Miscellaneous Output Register 0 */ +#define TMC_ITTRFLIN 0xEE8 /* Integration Test Trigger In and Flush In Register */ +#define TMC_ITATBDATA0 0xEEC /* Integration Test ATB Data Register 0 */ +#define TMC_ITATBCTR2 0xEF0 /* Integration Test ATB Control 2 Register */ +#define TMC_ITATBCTR1 0xEF4 /* Integration Test ATB Control 1 Register */ +#define TMC_ITATBCTR0 0xEF8 /* Integration Test ATB Control 0 Register */ +#define TMC_ITCTRL 0xF00 /* Integration Mode Control Register */ +#define TMC_CLAIMSET 0xFA0 /* Claim Tag Set Register */ +#define TMC_CLAIMCLR 0xFA4 /* Claim Tag Clear Register */ +#define TMC_LAR 0xFB0 /* Lock Access Register */ +#define TMC_LSR 0xFB4 /* Lock Status Register */ +#define TMC_AUTHSTATUS 0xFB8 /* Authentication Status Register */ +#define TMC_DEVID 0xFC8 /* Device Configuration Register */ +#define DEVID_CONFIGTYPE_S 6 +#define DEVID_CONFIGTYPE_M (0x3 << DEVID_CONFIGTYPE_S) +#define DEVID_CONFIGTYPE_ETB (0 << DEVID_CONFIGTYPE_S) +#define DEVID_CONFIGTYPE_ETR (1 << DEVID_CONFIGTYPE_S) +#define DEVID_CONFIGTYPE_ETF (2 << DEVID_CONFIGTYPE_S) +#define TMC_DEVTYPE 0xFCC /* Device Type Identifier Register */ +#define TMC_PERIPHID4 0xFD0 /* Peripheral ID4 Register */ +#define TMC_PERIPHID5 0xFD4 /* Peripheral ID5 Register */ +#define TMC_PERIPHID6 0xFD8 /* Peripheral ID6 Register */ +#define TMC_PERIPHID7 0xFDC /* Peripheral ID7 Register */ +#define TMC_PERIPHID0 0xFE0 /* Peripheral ID0 Register */ +#define TMC_PERIPHID1 0xFE4 /* Peripheral ID1 Register */ +#define TMC_PERIPHID2 0xFE8 /* Peripheral ID2 Register */ +#define TMC_PERIPHID3 0xFEC /* Peripheral ID3 Register */ +#define TMC_COMPID0 0xFF0 /* Component ID0 Register */ +#define TMC_COMPID1 0xFF4 /* Component ID1 Register */ +#define TMC_COMPID2 0xFF8 /* Component ID2 Register */ +#define TMC_COMPID3 0xFFC /* Component ID3 Register */ + +#endif /* !_ARM64_CORESIGHT_CORESIGHT_TMC_H_ */ Modified: head/sys/conf/files.arm64 ============================================================================== --- head/sys/conf/files.arm64 Tue Jun 9 15:17:23 2020 (r361967) +++ head/sys/conf/files.arm64 Tue Jun 9 15:56:41 2020 (r361968) @@ -187,12 +187,12 @@ arm64/cloudabi32/cloudabi32_sysvec.c optional compat_c arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard -arm64/coresight/coresight-cmd.c standard -arm64/coresight/coresight-cpu-debug.c standard -arm64/coresight/coresight-dynamic-replicator.c standard -arm64/coresight/coresight-etm4x.c standard -arm64/coresight/coresight-funnel.c standard -arm64/coresight/coresight-tmc.c standard +arm64/coresight/coresight_cmd.c standard +arm64/coresight/coresight_cpu_debug.c standard +arm64/coresight/coresight_dynamic_replicator.c standard +arm64/coresight/coresight_etm4x.c standard +arm64/coresight/coresight_funnel.c standard +arm64/coresight/coresight_tmc.c standard arm64/intel/firmware.c optional soc_intel_stratix10 arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 arm64/intel/stratix10-svc.c optional soc_intel_stratix10
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