jwGTy3TsYHmMc9e3512ITRWTW/3F/Fyq4f I2lnuPorM8NWLy4+R8m1EOie9FiL1z3JmSKtd6+cw/1tOUDKEbroRTPvQ0yc66zwxq1kYN sbkDXMsKK0/JXQZUTMrsnqF4kM+ceSCq3aLWFXVeaCebPwyMFkYj/zQp4kkH74ilLV7JZC wBg7Iyu7FqFYOkmyWOI0Y1UTFf+cp4PNu9SGFy/P2WvNYRrYlHtgN74zJw8u5A== ARC-Authentication-Results: i=1; mx1.freebsd.org; none Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4dyPQv2RkKzBgm for ; Fri, 23 Jan 2026 17:03:51 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 3767f by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Fri, 23 Jan 2026 17:03:51 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 6c5fdba45a63 - main - arm/gic: Detect broken configurations List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 6c5fdba45a63d66984e15ddc6996f5e88a55f22c Auto-Submitted: auto-generated Date: Fri, 23 Jan 2026 17:03:51 +0000 Message-Id: <6973a9f7.3767f.22208c22@gitrepo.freebsd.org> The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=6c5fdba45a63d66984e15ddc6996f5e88a55f22c commit 6c5fdba45a63d66984e15ddc6996f5e88a55f22c Author: Andrew Turner AuthorDate: 2026-01-23 14:31:04 +0000 Commit: Andrew Turner CommitDate: 2026-01-23 17:02:29 +0000 arm/gic: Detect broken configurations Some virtualization platforms provide broken configurations. There is a GIC interrupt controller, however accessing the CPU interface registers leads to an external data abort. As these are needed to handle interrupts we are unable to boot further. Detect this misconfiguration and panic to tell the user the issue. Reviewed by: emaste Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D54832 --- sys/arm/arm/gic.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/sys/arm/arm/gic.c b/sys/arm/arm/gic.c index e33bda4886b9..64f19c848ea2 100644 --- a/sys/arm/arm/gic.c +++ b/sys/arm/arm/gic.c @@ -151,6 +151,8 @@ static struct arm_gic_softc *gic_sc = NULL; /* CPU Interface */ #define gic_c_read_4(_sc, _reg) \ bus_read_4((_sc)->gic_res[GIC_RES_CPU], (_reg)) +#define gic_c_peek_4(_sc, _reg, _val) \ + bus_peek_4((_sc)->gic_res[GIC_RES_CPU], (_reg), (_val)) #define gic_c_write_4(_sc, _reg, _val) \ bus_write_4((_sc)->gic_res[GIC_RES_CPU], (_reg), (_val)) /* Distributor Interface */ @@ -347,7 +349,18 @@ arm_gic_attach(device_t dev) goto cleanup; } - icciidr = gic_c_read_4(sc, GICC_IIDR); + /* + * Try accessing a CPU interface register. On some broken + * virtualization environments this will raise an external + * data abort. When this happens we can detect it using + * by peeking at the register & checking for the fault. + * As there is no way to continue with a normal boot we + * panic. + */ + if (gic_c_peek_4(sc, GICC_IIDR, &icciidr) != 0) + panic("Unable to access %s CPU registers, " + "broken hardware or hypervisor configuration", + device_get_nameunit(dev)); device_printf(dev, "pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n", GICD_IIDR_PROD(icciidr), GICD_IIDR_VAR(icciidr),