From owner-freebsd-current Fri Feb 19 19:12:20 1999 Delivered-To: freebsd-current@freebsd.org Received: from smtp01.primenet.com (smtp01.primenet.com [206.165.6.131]) by hub.freebsd.org (Postfix) with ESMTP id AB06F10E59 for ; Fri, 19 Feb 1999 19:12:17 -0800 (PST) (envelope-from tlambert@usr02.primenet.com) Received: (from daemon@localhost) by smtp01.primenet.com (8.8.8/8.8.8) id UAA01685; Fri, 19 Feb 1999 20:12:16 -0700 (MST) Received: from usr02.primenet.com(206.165.6.202) via SMTP by smtp01.primenet.com, id smtpd001639; Fri Feb 19 20:12:13 1999 Received: (from tlambert@localhost) by usr02.primenet.com (8.8.5/8.8.5) id UAA25219; Fri, 19 Feb 1999 20:12:12 -0700 (MST) From: Terry Lambert Message-Id: <199902200312.UAA25219@usr02.primenet.com> Subject: Re: AMD K6-2 for smp To: idiotswitch@beer.com Date: Sat, 20 Feb 1999 03:12:12 +0000 (GMT) Cc: current@FreeBSD.ORG In-Reply-To: <002001be5bfe$f3d9a360$0a00000a@a19.my.intranet> from "IdiotSwitch Editor" at Feb 19, 99 06:56:54 am X-Mailer: ELM [version 2.4 PL25] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Sender: owner-freebsd-current@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG > I understand that you can purchase special motherboards (probably only from > AMD) for SMP K6-2's (possibly they'll take -3's as well). I doubt (without > trying) the freebsd code supports this style as it's not done in the normal > fashion. They kind of cheated the chips into working together. Not a great > system. Either get a twin PII, or wait for the K7's (but that won't be > cheap). It is my understanding that the K7's require "OpenAPIC". The SMP code would need to be updated for the non-APIC based implementation for the K7's. It's also my understanding that the K6 SMP architectures use the "BeBox" PPC 603 SMP hack (the PPC 604's used in the SMP Apple boxes have "processor attention" pins, and so don't suffer this handicap). The hack involves using an ASIC in place of the L2 cache controllers that would normally be associated with the chip. The result is that the combined system supports only MEI cache coherency, instead of MESI cache coherency. FreeBSD's SMP really, really depends on MESI. Really. This means that it would be very hard to port a working SMP over to another architecture (e.g. SPARC, like Linux has), without abstracting the cache coherency code out as a seperate (NULL on Intel) layer. In many ways, it was bad to do SMP on Intel MPSpec compatible hardware, instead of starting with lesser hardware and porting, since the implementation is tied to the spec (for now). Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-current" in the body of the message