From owner-freebsd-hackers@FreeBSD.ORG Mon May 12 17:39:17 2008 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 1CAB21065670 for ; Mon, 12 May 2008 17:39:17 +0000 (UTC) (envelope-from fbsd06+V3=62d9fb26@mlists.homeunix.com) Received: from turtle-out.mxes.net (turtle-out.mxes.net [216.86.168.191]) by mx1.freebsd.org (Postfix) with ESMTP id B4FBC8FC0C for ; Mon, 12 May 2008 17:39:16 +0000 (UTC) (envelope-from fbsd06+V3=62d9fb26@mlists.homeunix.com) Received: from mxout-03.mxes.net (mxout-03.mxes.net [216.86.168.178]) by turtle-in.mxes.net (Postfix) with ESMTP id 43511163F74 for ; Mon, 12 May 2008 13:23:42 -0400 (EDT) Received: from gumby.homeunix.com. (unknown [87.81.140.128]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.mxes.net (Postfix) with ESMTP id 5CBB823E3FA for ; Mon, 12 May 2008 13:23:38 -0400 (EDT) Date: Mon, 12 May 2008 18:23:28 +0100 From: RW To: freebsd-hackers@freebsd.org Message-ID: <20080512182328.09a8a173@gumby.homeunix.com.> In-Reply-To: <4828557B.9000506@icyb.net.ua> References: <4828557B.9000506@icyb.net.ua> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.12.9; i386-portbld-freebsd7.0) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: i386 cpu_reset_real: code/comment mismatch X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 May 2008 17:39:17 -0000 On Mon, 12 May 2008 17:34:35 +0300 Andriy Gapon wrote: > > This is not a real issue, just a code clarification. > > First a snippet from sys/i386/i386/vm_machdep.c, cpu_reset_real() > /* > * Attempt to force a reset via the Reset Control register at > * I/O port 0xcf9. Bit 2 forces a system reset when it is > * written as 1. Bit 1 selects the type of reset to attempt: > * 0 selects a "soft" reset, and 1 selects a "hard" reset. We > * try to do a "soft" reset first, and then a "hard" reset. > */ > outb(0xcf9, 0x2); > outb(0xcf9, 0x6); > > I think that the comment is correct up to but not including the last > sentence. Writing 0x2 sets bit 1 to 1 (thus selecting hard reset), and > writing 0x6 sets both bits 2 and 1 to 1 (thus performing hard reset). > So we always just do a hard reset, no trying of soft reset (would it > even make sense to do the last line of the comment says). > It looks to me as if the comment was added retrospectively by someone who got the two bits mixed-up when reading the source. If bits 1 and 2 were the other way around, it would be code for a soft-reset followed by a hard-reset.