From owner-cvs-src-old@FreeBSD.ORG Mon Jul 6 18:23:47 2009 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CC34A106567F for ; Mon, 6 Jul 2009 18:23:47 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id B91CF8FC1F for ; Mon, 6 Jul 2009 18:23:47 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n66INlWa097307 for ; Mon, 6 Jul 2009 18:23:47 GMT (envelope-from jhb@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n66INlj5097306 for cvs-src-old@freebsd.org; Mon, 6 Jul 2009 18:23:47 GMT (envelope-from jhb@repoman.freebsd.org) Message-Id: <200907061823.n66INlj5097306@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to jhb@repoman.freebsd.org using -f From: John Baldwin Date: Mon, 6 Jul 2009 18:23:00 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/amd64/amd64 io_apic.c msi.c src/sys/i386/i386 io_apic.c msi.c X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Jul 2009 18:23:48 -0000 jhb 2009-07-06 18:23:00 UTC FreeBSD src repository Modified files: sys/amd64/amd64 io_apic.c msi.c sys/i386/i386 io_apic.c msi.c Log: SVN rev 195415 on 2009-07-06 18:23:00Z by jhb After the per-CPU IDT changes, the IDT vector of an interrupt could change when the interrupt was moved from one CPU to another. If the interrupt was enabled, then the old IDT vector needs to be disabled and the new IDT vector needs to be enabled. This was mostly masked prior to the recent MSI changes since in the older code almost all allocated IDT vectors were already enabled and the enabled vectors on the BSP during boot covered enough of the IDT range. However, after the MSI changes, MSI interrupts that were allocated but not enabled (e.g. DRM with MSI) during boot could result in an allocated IDT vector that wasn't enabled. The round-robin at the end of boot could place another interrupt at the same IDT vector without enabling the IDT vector causing trap 30 faults. Fix this by explicitly disabling/enabling the old and new IDT vectors for enabled interrupt sources when moving an interrupt between CPUs via the pic_assign_cpu() method. While here, fix a bug in my earlier changes so that an I/O APIC interrupt pin is left unchanged if ioapic_assign_cpu() fails to allocate a new IDT vector and returns ENOSPC. Approved by: re (kensmith) Revision Changes Path 1.35 +11 -5 src/sys/amd64/amd64/io_apic.c 1.14 +11 -1 src/sys/amd64/amd64/msi.c 1.39 +11 -5 src/sys/i386/i386/io_apic.c 1.14 +11 -1 src/sys/i386/i386/msi.c