Date: Sat, 7 Feb 2015 23:25:57 +0000 (UTC) From: Dimitry Andric <dim@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r278367 - projects/clang360-import/contrib/llvm/lib/Target/Mips Message-ID: <201502072325.t17NPvTf076052@svn.freebsd.org>
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Author: dim Date: Sat Feb 7 23:25:56 2015 New Revision: 278367 URL: https://svnweb.freebsd.org/changeset/base/278367 Log: Pull in r227089 from upstream llvm trunk (by Vasileios Kalintiris): [mips] Enable arithmetic and binary operations for the i128 data type. Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 This fixes "error in backend" messages, when compiling parts of compiler-rt using 128-bit integer types for mips64. Reported by: sbruno PR: 197259 Modified: projects/clang360-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp Modified: projects/clang360-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td ============================================================================== --- projects/clang360-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td Sat Feb 7 23:11:38 2015 (r278366) +++ projects/clang360-import/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td Sat Feb 7 23:25:56 2015 (r278367) @@ -440,6 +440,16 @@ def : MipsPat<(i64 (sext_inreg GPR64:$sr // bswap MipsPattern def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; +// Carry pattern +def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs), + (DSUBu GPR64:$lhs, GPR64:$rhs)>; +let AdditionalPredicates = [NotDSP] in { + def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs), + (DADDu GPR64:$lhs, GPR64:$rhs)>; + def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm), + (DADDiu GPR64:$lhs, imm:$imm)>; +} + //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// Modified: projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp ============================================================================== --- projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp Sat Feb 7 23:11:38 2015 (r278366) +++ projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp Sat Feb 7 23:25:56 2015 (r278367) @@ -261,6 +261,9 @@ MipsTargetLowering::MipsTargetLowering(c setOperationAction(ISD::LOAD, MVT::i64, Custom); setOperationAction(ISD::STORE, MVT::i64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); + setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); } if (!Subtarget.isGP64bit()) { @@ -2017,10 +2020,11 @@ SDValue MipsTargetLowering::lowerATOMIC_ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); + MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; + SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); SDValue Shamt = Op.getOperand(2); - - // if shamt < 32: + // if shamt < (VT.bits): // lo = (shl lo, shamt) // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) // else: @@ -2028,18 +2032,17 @@ SDValue MipsTargetLowering::lowerShiftLe // hi = (shl lo, shamt[4:0]) SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32)); - SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, - DAG.getConstant(1, MVT::i32)); - SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, ShiftRight1Lo, - Not); - SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, Shamt); - SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); - SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, MVT::i32, Lo, Shamt); + SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, + DAG.getConstant(1, VT)); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); + SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(0x20, MVT::i32)); - Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, - DAG.getConstant(0, MVT::i32), ShiftLeftLo); - Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftLeftLo, Or); + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, + DAG.getConstant(0, VT), ShiftLeftLo); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or); SDValue Ops[2] = {Lo, Hi}; return DAG.getMergeValues(Ops, DL); @@ -2050,8 +2053,9 @@ SDValue MipsTargetLowering::lowerShiftRi SDLoc DL(Op); SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); SDValue Shamt = Op.getOperand(2); + MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; - // if shamt < 32: + // if shamt < (VT.bits): // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) // if isSRA: // hi = (sra hi, shamt) @@ -2066,21 +2070,19 @@ SDValue MipsTargetLowering::lowerShiftRi // hi = 0 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, DAG.getConstant(-1, MVT::i32)); - SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, MVT::i32, Hi, - DAG.getConstant(1, MVT::i32)); - SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, MVT::i32, ShiftLeft1Hi, Not); - SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, MVT::i32, Lo, Shamt); - SDValue Or = DAG.getNode(ISD::OR, DL, MVT::i32, ShiftLeftHi, ShiftRightLo); - SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, DL, MVT::i32, - Hi, Shamt); + SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, + DAG.getConstant(1, VT)); + SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); + SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); + SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); + SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL, + DL, VT, Hi, Shamt); SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt, DAG.getConstant(0x20, MVT::i32)); - SDValue Shift31 = DAG.getNode(ISD::SRA, DL, MVT::i32, Hi, - DAG.getConstant(31, MVT::i32)); - Lo = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, ShiftRightHi, Or); - Hi = DAG.getNode(ISD::SELECT, DL, MVT::i32, Cond, - IsSRA ? Shift31 : DAG.getConstant(0, MVT::i32), - ShiftRightHi); + SDValue Shift31 = DAG.getNode(ISD::SRA, DL, VT, Hi, DAG.getConstant(31, VT)); + Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or); + Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, + IsSRA ? Shift31 : DAG.getConstant(0, VT), ShiftRightHi); SDValue Ops[2] = {Lo, Hi}; return DAG.getMergeValues(Ops, DL); Modified: projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp ============================================================================== --- projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sat Feb 7 23:11:38 2015 (r278366) +++ projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp Sat Feb 7 23:25:56 2015 (r278367) @@ -236,13 +236,31 @@ SDNode *MipsSEDAGToDAGISel::selectAddESu (Opc == ISD::SUBC || Opc == ISD::SUBE)) && "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn"); + unsigned SLTuOp = Mips::SLTu, ADDuOp = Mips::ADDu; + if (Subtarget->isGP64bit()) { + SLTuOp = Mips::SLTu64; + ADDuOp = Mips::DADDu; + } + SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) }; SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1); EVT VT = LHS.getValueType(); - SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops); - SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT, + SDNode *Carry = CurDAG->getMachineNode(SLTuOp, DL, VT, Ops); + + if (Subtarget->isGP64bit()) { + // On 64-bit targets, sltu produces an i64 but our backend currently says + // that SLTu64 produces an i32. We need to fix this in the long run but for + // now, just make the DAG type-correct by asserting the upper bits are zero. + Carry = CurDAG->getMachineNode(Mips::SUBREG_TO_REG, DL, VT, + CurDAG->getTargetConstant(0, VT), + SDValue(Carry, 0), + CurDAG->getTargetConstant(Mips::sub_32, VT)); + } + + SDNode *AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS); + return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS, SDValue(AddCarry, 0)); } @@ -641,7 +659,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGI case ISD::SUBE: { SDValue InFlag = Node->getOperand(2); - Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node); + unsigned Opc = Subtarget->isGP64bit() ? Mips::DSUBu : Mips::SUBu; + Result = selectAddESubE(Opc, InFlag, InFlag.getOperand(0), DL, Node); return std::make_pair(true, Result); } @@ -649,7 +668,8 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGI if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC. break; SDValue InFlag = Node->getOperand(2); - Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node); + unsigned Opc = Subtarget->isGP64bit() ? Mips::DADDu : Mips::ADDu; + Result = selectAddESubE(Opc, InFlag, InFlag.getValue(0), DL, Node); return std::make_pair(true, Result); } Modified: projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp ============================================================================== --- projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp Sat Feb 7 23:11:38 2015 (r278366) +++ projects/clang360-import/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp Sat Feb 7 23:25:56 2015 (r278367) @@ -122,6 +122,8 @@ MipsSETargetLowering::MipsSETargetLoweri setOperationAction(ISD::MUL, MVT::i64, Custom); if (Subtarget.isGP64bit()) { + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom); + setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom); setOperationAction(ISD::MULHS, MVT::i64, Custom); setOperationAction(ISD::MULHU, MVT::i64, Custom); setOperationAction(ISD::SDIVREM, MVT::i64, Custom); @@ -200,6 +202,8 @@ MipsSETargetLowering::MipsSETargetLoweri if (Subtarget.hasMips64r6()) { // MIPS64r6 replaces the accumulator-based multiplies with a three register // instruction + setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); setOperationAction(ISD::MUL, MVT::i64, Legal); setOperationAction(ISD::MULHS, MVT::i64, Legal); setOperationAction(ISD::MULHU, MVT::i64, Legal);
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