From owner-cvs-src@FreeBSD.ORG Thu Oct 20 11:11:43 2005 Return-Path: X-Original-To: cvs-src@freebsd.org Delivered-To: cvs-src@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A550F16A41F; Thu, 20 Oct 2005 11:11:43 +0000 (GMT) (envelope-from bde@zeta.org.au) Received: from mailout1.pacific.net.au (mailout1.pacific.net.au [61.8.0.84]) by mx1.FreeBSD.org (Postfix) with ESMTP id F164643D69; Thu, 20 Oct 2005 11:11:42 +0000 (GMT) (envelope-from bde@zeta.org.au) Received: from mailproxy1.pacific.net.au (mailproxy1.pacific.net.au [61.8.0.86]) by mailout1.pacific.net.au (8.13.4/8.13.4/Debian-3) with ESMTP id j9KBBNAI017674; Thu, 20 Oct 2005 21:11:23 +1000 Received: from katana.zip.com.au (katana.zip.com.au [61.8.7.246]) by mailproxy1.pacific.net.au (8.13.4/8.13.4/Debian-3) with ESMTP id j9KBBB9X021798; Thu, 20 Oct 2005 21:11:11 +1000 Date: Thu, 20 Oct 2005 21:11:11 +1000 (EST) From: Bruce Evans X-X-Sender: bde@delplex.bde.org To: David Xu In-Reply-To: <435749A8.5070309@freebsd.org> Message-ID: <20051020205717.R874@delplex.bde.org> References: <200510172310.j9HNAVPL013057@repoman.freebsd.org> <20051018094402.A29138@grasshopper.cs.duke.edu> <435501B9.4070401@samsco.org> <17237.1482.52148.283282@grasshopper.cs.duke.edu> <4355080C.302@samsco.org> <20051020145234.H99720@delplex.bde.org> <435749A8.5070309@freebsd.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed Cc: cvs-src@freebsd.org, Scott Long , src-committers@freebsd.org, Andrew Gallatin , cvs-all@freebsd.org Subject: Re: cvs commit: src/sys/amd64/amd64 cpu_switch.S machdep.c X-BeenThere: cvs-src@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 20 Oct 2005 11:11:43 -0000 On Thu, 20 Oct 2005, David Xu wrote: > Bruce Evans wrote: >> I wonder if this reduces the context switch latency from about 1.320 >> usec to 0.900 usec on my A64-3000. The latency is only .520 usec in >> i386 mode. I use a TSC timecounter of course. > > we can avoid reloading userland GS.base MSR and FS.base MSR for system > threads, I am not sure if it can reduce interrupt thread latency. I think it would recover some of the the other 0.400 usec of the extra overhead for the amd64 case. We already avoid null reloads of %cr3 and avoiding null reloads of FS/GS.base would be similar. Both are null only for intra-kernel switches, so the savings are smaller than for the stores of FS/GS.base since the reloads can't always be avoided. Bruce