From owner-freebsd-hackers Thu Feb 27 08:12:14 1997 Return-Path: Received: (from root@localhost) by freefall.freebsd.org (8.8.5/8.8.5) id IAA04557 for hackers-outgoing; Thu, 27 Feb 1997 08:12:14 -0800 (PST) Received: from usr11.primenet.com (root@usr11.primenet.com [206.165.5.111]) by freefall.freebsd.org (8.8.5/8.8.5) with ESMTP id IAA04552 for ; Thu, 27 Feb 1997 08:12:10 -0800 (PST) Received: from primenet.com (root@mailhost01.primenet.com [206.165.5.52]) by usr11.primenet.com (8.8.5/8.8.5) with ESMTP id JAA11245; Thu, 27 Feb 1997 09:11:20 -0700 (MST) Received: from conceptual.com (consys.com [207.218.17.187]) by primenet.com (8.8.5/8.8.5) with ESMTP id JAA07965; Thu, 27 Feb 1997 09:11:15 -0700 (MST) Received: from conceptual.com (localhost [127.0.0.1]) by conceptual.com (8.8.5/8.6.9) with ESMTP id JAA15971; Thu, 27 Feb 1997 09:11:08 -0700 (MST) Message-Id: <199702271611.JAA15971@conceptual.com> X-Mailer: exmh version 2.0gamma 1/27/96 To: mika ruohotie cc: hfwirth@ping.at (Helmut F. Wirth), freebsd-hackers@freebsd.org Subject: Re: Pentium MMX Extensions, Changes to (g)as and gdb In-reply-to: Your message of "Thu, 27 Feb 1997 11:23:10 +0200." <199702270923.LAA07796@shadows.aeon.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 27 Feb 1997 09:11:08 -0700 From: "Russell L. Carter" Sender: owner-hackers@freebsd.org X-Loop: FreeBSD.org Precedence: bulk > > Hello, > > I made some changes to gas and gdb to support the new MMX extensions > > for the Pentium P55C. > > gee, cool. i didnt think we'd something about that this fast... > > what i'm interested in is, does the mmx cpu run normal freebsd any > faster? the 'make world' is probably the only thing one could use > for measuring it in the "reality" level... i would assume just coz of > larger L1 cache it is already faster. > The MMX instructions themselves will not affect the speed of anything resembling a "normal" code. Intel's P5 cpus with MMX run faster because they have a 2x bigger level1 cache and a few of the scheduling enhancements that first showed up in P6. Interestingly, the P6++ cpus with MMX (so-called Pentium II) run slower than P6 at the same clock rate because of the psuedo-on-chip level2 cache. It's conceivable that pd libraries could start showing up that use these instructions in specific assembly coded routines. I like the idea of putting the MMX instructions in though. Russell