From owner-svn-src-head@FreeBSD.ORG Thu Oct 22 16:22:00 2009 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8D95B1065672; Thu, 22 Oct 2009 16:22:00 +0000 (UTC) (envelope-from xcllnt@mac.com) Received: from asmtpout029.mac.com (asmtpout029.mac.com [17.148.16.104]) by mx1.freebsd.org (Postfix) with ESMTP id 72B8A8FC1A; Thu, 22 Oct 2009 16:22:00 +0000 (UTC) MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; charset=us-ascii; format=flowed; delsp=yes Received: from macbook-pro.jnpr.net (natint3.juniper.net [66.129.224.36]) by asmtp029.mac.com (Sun Java(tm) System Messaging Server 6.3-8.01 (built Dec 16 2008; 32bit)) with ESMTPSA id <0KRX004BLC45YI80@asmtp029.mac.com>; Thu, 22 Oct 2009 09:21:46 -0700 (PDT) From: Marcel Moolenaar In-reply-to: Date: Thu, 22 Oct 2009 09:21:40 -0700 Message-id: <97E86964-5F25-4C03-8A04-FBC65345234D@mac.com> References: <200910211838.n9LIc2wp007206@svn.freebsd.org> To: Rafal Jaworowski X-Mailer: Apple Mail (2.1076) Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, Marcel Moolenaar , src-committers@freebsd.org Subject: Re: svn commit: r198341 - in head/sys: amd64/amd64 arm/arm arm/mv i386/i386 i386/xen ia64/ia64 kern mips/mips powerpc/aim powerpc/booke powerpc/include powerpc/powerpc sparc64/sparc64 sun4v/sun4v vm X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 22 Oct 2009 16:22:00 -0000 On Oct 22, 2009, at 2:10 AM, Rafal Jaworowski wrote: > > On 2009-10-21, at 20:38, Marcel Moolenaar wrote: > >> The key property of this change is that the I-cache is made coherent >> *after* writes have been done. Doing it in the PMAP layer when adding >> or changing a mapping means that the I-cache is made coherent >> *before* >> any writes happen. The difference is key when the I-cache prefetches. > > Marcel, does this new approach help with your problems on MV-78xxx > with SATA when executing binaries was failing with various signals > etc. (and the suspicions were this was due to some i-cache > incoherency)? This commit only adds I-cache synchronisation to ptrace(2) so that breakpoints work reliably. Note that the PMAP layer for ARM needs to have a proper implementation, because breakpoints don't work reliably. Unfortunately, the PMAP code is not well suited for non-current PMAP operations. I'm looking into it... In any case: I'll be working on moving I-cache coherency from PMAP to MI where sensible to make sure we synchronize after the memory update and not before (or multiple times in an attempt to plaster over the cracks). I expect that in the end it'll have helped... :-) -- Marcel Moolenaar xcllnt@mac.com