From owner-p4-projects@FreeBSD.ORG Thu Jan 8 16:30:30 2009 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id 4BC221065672; Thu, 8 Jan 2009 16:30:30 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 0B127106566B for ; Thu, 8 Jan 2009 16:30:30 +0000 (UTC) (envelope-from nwhitehorn@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id EDB1C8FC19 for ; Thu, 8 Jan 2009 16:30:29 +0000 (UTC) (envelope-from nwhitehorn@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n08GUTXY038485 for ; Thu, 8 Jan 2009 16:30:29 GMT (envelope-from nwhitehorn@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n08GUTeT038483 for perforce@freebsd.org; Thu, 8 Jan 2009 16:30:29 GMT (envelope-from nwhitehorn@freebsd.org) Date: Thu, 8 Jan 2009 16:30:29 GMT Message-Id: <200901081630.n08GUTeT038483@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to nwhitehorn@freebsd.org using -f From: Nathan Whitehorn To: Perforce Change Reviews Cc: Subject: PERFORCE change 155823 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jan 2009 16:30:31 -0000 http://perforce.freebsd.org/chv.cgi?CH=155823 Change 155823 by nwhitehorn@nwhitehorn_trantor on 2009/01/08 16:30:00 970 CPUs don't implement the L2 and L3 cache configuration registers, so we should not try to program them. We should have a better scheme (a CPU features mask) for controlling this -- right now we just check if the stored values for the L2CR and L3CR are zero. This commit makes SMP work in the simulator, modulo platform-specific issues starting the CPU. It may work on real (Apple) hardware. The CPU start/stop bits of this file should be abstracted into a platform module. Affected files ... .. //depot/projects/ppc-g5/sys/powerpc/aim/mp_cpudep.c#3 edit Differences ... ==== //depot/projects/ppc-g5/sys/powerpc/aim/mp_cpudep.c#3 (text+ko) ==== @@ -250,8 +250,10 @@ mtmsr(msr); isync(); - reg = l3_enable(); - reg = l2_enable(); + if (l3cr_config != 0) + reg = l3_enable(); + if (l2cr_config != 0) + reg = l2_enable(); reg = l1d_enable(); reg = l1i_enable();