Date: Wed, 30 Jul 2008 12:40:03 GMT From: Mark Willson <mark@hydrus.org.uk> To: freebsd-net@FreeBSD.org Subject: Re: kern/112179: [sis] [patch] sis driver for natsemi DP83815D autonegotiate failure Message-ID: <200807301240.m6UCe3mM063649@freefall.freebsd.org>
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The following reply was made to PR kern/112179; it has been noted by GNATS.
From: Mark Willson <mark@hydrus.org.uk>
To: bug-followup@FreeBSD.org, jhb@FreeBSD.org
Cc: phk@FreeBSD.org
Subject: Re: kern/112179: [sis] [patch] sis driver for natsemi DP83815D autonegotiate failure
Date: Wed, 30 Jul 2008 13:04:59 +0100 (BST)
> From: John Baldwin <jhb@FreeBSD.org>
> Subject: Re: kern/112179: [sis] [patch] sis driver for natsemi DP83815D
> autonegotiate failure
> Date: Tue, 29 Jul 2008 11:56:38 -0400
> Cc: phk@FreeBSD.org
>
> How about the patch below. This makes the driver match the behavior of the
> Linux driver (and also fixes a harmless weirdness phk@ introduced.. I think
> because he thought SIS_SETBIT was CSR_WRITE_4 rather than a RMW op).
>
> Index: if_sis.c
> ===================================================================
> --- if_sis.c (revision 180877)
> +++ if_sis.c (working copy)
> @@ -1904,14 +1904,15 @@
> if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
> CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
> CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
> - if (sc->sis_srr == NS_SRR_15C) {
> - /* set val for c2 */
> - CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
> + /* set val for c2 */
> + CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
> + if (sc->sis_srr <= NS_SRR_15C)
> /* load/kill c2 */
> CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
> - /* rais SD off, from 4 to c */
> - CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
> - }
> + else
> + SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x1000);
> + /* rais SD off, from 4 to c */
> + CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
> CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
> }
>
> @@ -2011,12 +2012,11 @@
> CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
> DELAY(100000);
> reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
> - if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
> + if ((reg & 0x0080) == 0 || (reg >= 0xd8 && reg <= 0xff)) {
> device_printf(sc->sis_dev,
> "Applying short cable fix (reg=%x)\n", reg);
> CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
> - reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
> - SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20);
> + SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
> }
> CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
> }
>
John,
Thanks for the patch. I tried it out on my system, but it did not fix
the problem. However, if I make a small change, it works fine.
It seems the call "CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);" is
necessary for the NS_SRR_15D revision of the card.
Here's the modified patch:
--- if_sis.c.orig 2008-07-30 11:04:53.000000000 +0100
+++ if_sis.c 2008-07-30 11:08:15.000000000 +0100
@@ -1904,14 +1904,14 @@
if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
- if (sc->sis_srr == NS_SRR_15C) {
- /* set val for c2 */
- CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
- /* load/kill c2 */
- CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
- /* rais SD off, from 4 to c */
- CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
- }
+ /* set val for c2 */
+ CSR_WRITE_4(sc, NS_PHY_TDATA, 0x0000);
+ /* load/kill c2 */
+ CSR_WRITE_4(sc, NS_PHY_DSPCFG, 0x5040);
+ if (sc->sis_srr > NS_SRR_15C)
+ SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x1000);
+ /* rais SD off, from 4 to c */
+ CSR_WRITE_4(sc, NS_PHY_SDCFG, 0x008C);
CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
}
@@ -2011,12 +2011,11 @@
CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
DELAY(100000);
reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
- if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
+ if ((reg & 0x0080) == 0 || (reg >= 0xd8 && reg <= 0xff)) {
device_printf(sc->sis_dev,
"Applying short cable fix (reg=%x)\n", reg);
CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
- reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
- SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20);
+ SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
}
CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
}
-mark
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