Date: Tue, 10 Jan 2012 14:39:57 -0700 From: Ian Lepore <freebsd@damnhippie.dyndns.org> To: Luigi Rizzo <rizzo@iet.unipi.it> Cc: FreeBSD current <freebsd-current@freebsd.org> Subject: Re: memory barriers in bus_dmamap_sync() ? Message-ID: <1326231597.2419.46.camel@revolution.hippie.lan> In-Reply-To: <20120110213719.GA92799@onelab2.iet.unipi.it> References: <20120110213719.GA92799@onelab2.iet.unipi.it>
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On Tue, 2012-01-10 at 22:37 +0100, Luigi Rizzo wrote: > I was glancing through manpages and implementations of bus_dma(9) > and i am a bit unclear on what this API (in particular, bus_dmamap_sync() ) > does in terms of memory barriers. > > I see that the x86/amd64 and ia64 code only does the bounce buffers. > The mips seems to do some coherency-related calls. > > How do we guarantee, say, that a recently built packet is > to memory before issuing the tx command to the NIC ? > > cheers > luigi I've always assumed that when the concept of a memory barrier means anything for a given architecture, it's implied that the bus_dmamap_sync() call has to invoke it as needed to ensure the DMA operation picks up the right data. Maybe it would be good if the manpage said that straight out. The ARM implementations do use the memory barrier operations, in the form of a call to cpu_drain_writebuf() in the busdma_machdep code. The ARM specification says that the CPU is stopped until all buffered data is written to memory for that operation. -- Ian
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