From owner-freebsd-isp Wed Feb 26 08:13:31 1997 Return-Path: Received: (from root@localhost) by freefall.freebsd.org (8.8.5/8.8.5) id IAA15309 for isp-outgoing; Wed, 26 Feb 1997 08:13:31 -0800 (PST) Received: from mx.serv.net (mx.serv.net [199.201.191.10]) by freefall.freebsd.org (8.8.5/8.8.5) with ESMTP id IAA15303; Wed, 26 Feb 1997 08:13:27 -0800 (PST) Received: from MindBender.serv.net by mx.serv.net (8.7.5/SERV Revision: 2.30) id IAA26301; Wed, 26 Feb 1997 08:13:18 -0800 (PST) Received: from localhost.HeadCandy.com (michaelv@localhost.HeadCandy.com [127.0.0.1]) by MindBender.serv.net (8.7.5/8.7.3) with SMTP id IAA03753; Wed, 26 Feb 1997 08:13:13 -0800 (PST) Message-Id: <199702261613.IAA03753@MindBender.serv.net> X-Authentication-Warning: MindBender.serv.net: Host michaelv@localhost.HeadCandy.com [127.0.0.1] didn't use HELO protocol To: Vincent Poy cc: Tom Samplonius , "Vnotchenko S.S." , freebsd-isp@freebsd.org, freebsd-hackers@freebsd.org Subject: Re: [H] Optimal computer for FreeBSD In-reply-to: Your message of Wed, 26 Feb 97 04:14:41 -0800. Date: Wed, 26 Feb 1997 08:13:12 -0800 From: "Michael L. VanLoon -- HeadCandy.com" Sender: owner-isp@freebsd.org X-Loop: FreeBSD.org Precedence: bulk >> > Always use parity RAM on servers, especially if you are buying >> >everything from scratch. >> > EDO doesn't give you much of a improvement if your motherboard supports >> >pipeline-burst-cache. >> My guess is that it doesn't, since the cache is built into the CPU... >> :-) > Actually, from what Rodney Grimes had told me, the cache built >into the CPU is the L1 (Level 1) cache while the L2 cache is the cache on >the motherboard, with Pipeline Burst Caching, it will give like the same Nope, you are completely wrong. Go read the specs for yourself sometime. You can find them at http://www.intel.com/. The Pentium Pro (sometimes known as the P6) has a dual-well carrier design that has both the L1 and the L2 cache in the "chip". I. e., there are two separate pieces of silicon, but they are both in the same package. There is no L3 cache on the motherboard. Note that the Klamath will be different. The L2 cache will not be in the same chip carrier. But it will not be on the "motherboard", either. The Klamath will be delivered in some kind of funky "cartridge" that contains the CPU, cache, and supposedly some other support circuitry. ----------------------------------------------------------------------------- Michael L. VanLoon michaelv@MindBender.serv.net --< Free your mind and your machine -- NetBSD free un*x >-- NetBSD working ports: 386+PC, Mac 68k, Amiga, Atari 68k, HP300, Sun3, Sun4/4c/4m, DEC MIPS, DEC Alpha, PC532, VAX, MVME68k, arm32... NetBSD ports in progress: PICA, others... -----------------------------------------------------------------------------