From owner-svn-src-stable-10@freebsd.org Mon Oct 12 13:20:18 2015 Return-Path: Delivered-To: svn-src-stable-10@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8CDDAA11478; Mon, 12 Oct 2015 13:20:18 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 3B16CF9A; Mon, 12 Oct 2015 13:20:18 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id t9CDKHK2098740; Mon, 12 Oct 2015 13:20:17 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id t9CDKHqt098739; Mon, 12 Oct 2015 13:20:17 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <201510121320.t9CDKHqt098739@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Mon, 12 Oct 2015 13:20:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r289184 - stable/10/sys/arm/mv X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-10@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for only the 10-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Oct 2015 13:20:18 -0000 Author: andrew Date: Mon Oct 12 13:20:17 2015 New Revision: 289184 URL: https://svnweb.freebsd.org/changeset/base/289184 Log: MFC of r288447. Only the Marvell driver has been updated as there is no support for Raspbetty Pi 2 in stable/10. An IPI must be cleared before it is handled otherwise next IPI could be missed. In other words, if a new request for an IPI is sent while the previous request is being handled but the IPI is not cleared yet, the clearing of the previous IPI request also clears the new one and the handling is missed. There are only three MP interrupt controllers in ARM now. Two of them are fixed by this change, the third one is correct, probably only just by accident. The fix is minimalistic as new interrupt framework is awaited. It was debugged on RPi2 where missing IPI handling together with SCHED_ULE led to situation in which tdq_ipipending was not cleared and so IPI_PREEMPT was stopped to be sent. Various odditys were found related to slow system response time like various events timed out, and slow console response. Modified: stable/10/sys/arm/mv/mpic.c Directory Properties: stable/10/ (props changed) Modified: stable/10/sys/arm/mv/mpic.c ============================================================================== --- stable/10/sys/arm/mv/mpic.c Mon Oct 12 10:44:20 2015 (r289183) +++ stable/10/sys/arm/mv/mpic.c Mon Oct 12 13:20:17 2015 (r289184) @@ -378,10 +378,14 @@ int pic_ipi_get(int i __unused) { uint32_t val; + int ipi; val = MPIC_CPU_READ(mv_mpic_sc, MPIC_IN_DRBL); - if (val) - return (ffs(val) - 1); + if (val) { + ipi = ffs(val) - 1; + MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, ~(1 << ipi)); + return (ipi); + } return (0x3ff); } @@ -389,10 +393,6 @@ pic_ipi_get(int i __unused) void pic_ipi_clear(int ipi) { - uint32_t val; - - val = ~(1 << ipi); - MPIC_CPU_WRITE(mv_mpic_sc, MPIC_IN_DRBL, val); } #endif