From owner-freebsd-hackers Thu Nov 7 14:39:31 1996 Return-Path: owner-hackers Received: (from root@localhost) by freefall.freebsd.org (8.7.5/8.7.3) id OAA21928 for hackers-outgoing; Thu, 7 Nov 1996 14:39:31 -0800 (PST) Received: from who.cdrom.com (who.cdrom.com [204.216.27.3]) by freefall.freebsd.org (8.7.5/8.7.3) with ESMTP id OAA21886 for ; Thu, 7 Nov 1996 14:39:25 -0800 (PST) Received: from pluto.plutotech.com (root@pluto.plutotech.com [206.168.67.1]) by who.cdrom.com (8.7.5/8.6.11) with ESMTP id KAA17675 for ; Thu, 7 Nov 1996 10:35:05 -0800 (PST) Received: from shane.plutotech.com (durian@shane.plutotech.com [206.168.67.21]) by pluto.plutotech.com (8.8.2/8.8.2) with ESMTP id LAA25115 for ; Thu, 7 Nov 1996 11:35:04 -0700 (MST) Message-Id: <199611071835.LAA25115@pluto.plutotech.com> From: "Mike Durian" To: freebsd-hackers@freebsd.org Subject: small bugs in pci code Date: Thu, 07 Nov 1996 11:35:09 -0700 Sender: owner-hackers@freebsd.org X-Loop: FreeBSD.org Precedence: bulk I've discovered three bugs in the pci code (at least I believe they are bugs). These are in the 2.1.5 release. Since we've made some local changes to these files, I don't have proper diffs, but the changes are very small and isolated. 1) In pcireg.h, the definitions of PCI_PPB_IOBASE_EXTRACT and PCI_PPB_IOLIMIT_EXTRACT should be: #define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xF000) #define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xF000) Notice the mask has changed from 0xff00 to 0xf000. This is because the lower nibble is not part of the address, but instead determines if the addressing is 16 bit or 32 bit. 2) Related to #1, the mask that is OR'd with the PCI_PPB_IOLIMIT_EXTRACT value should be 0xfff. It should not be calculated from the amount of memory requested. I don't have a line number for this, but it is in pci.c near the PCI_PPB_IOLIMIT_EXTRACT string, which only occurs once. The PCI standard says, "the upper 4 bits of I/O Limit register are writeable and correspond to address bits AD[15::12]. For purpose of address decoding the bridge assumes that the lower 12 address bits, AD[11::0], of the I/O limit address (not implemented in the I/O Limit register) are FFFh." 3) In the same pci_bus_config() function, there is a section of for loop code that begins with the comment, "Read the current mapping, and update the pcicb fields." In this for loop, there is a switch statement that handles the two types of mapping: I/O and memory. The line: switch (data & 7) { should read: switch (map & 7) { The lower three bits that determine the mapping type are found in the address value, not the size value. mike