From owner-svn-src-all@freebsd.org Wed May 29 02:08:24 2019 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 483A015B310C; Wed, 29 May 2019 02:08:24 +0000 (UTC) (envelope-from pfg@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id E24FD7498D; Wed, 29 May 2019 02:08:23 +0000 (UTC) (envelope-from pfg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id B767222FE1; Wed, 29 May 2019 02:08:23 +0000 (UTC) (envelope-from pfg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x4T28N5c045877; Wed, 29 May 2019 02:08:23 GMT (envelope-from pfg@FreeBSD.org) Received: (from pfg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x4T28NlQ045875; Wed, 29 May 2019 02:08:23 GMT (envelope-from pfg@FreeBSD.org) Message-Id: <201905290208.x4T28NlQ045875@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: pfg set sender to pfg@FreeBSD.org using -f From: "Pedro F. Giffuni" Date: Wed, 29 May 2019 02:08:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r348349 - in head: lib/libc/net sys/i386/i386 X-SVN-Group: head X-SVN-Commit-Author: pfg X-SVN-Commit-Paths: in head: lib/libc/net sys/i386/i386 X-SVN-Commit-Revision: 348349 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: E24FD7498D X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.95 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_SHORT(-0.95)[-0.952,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US]; NEURAL_HAM_LONG(-1.00)[-1.000,0] X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 29 May 2019 02:08:24 -0000 Author: pfg Date: Wed May 29 02:08:23 2019 New Revision: 348349 URL: https://svnweb.freebsd.org/changeset/base/348349 Log: typo: suppported. Modified: head/lib/libc/net/rthdr.c head/sys/i386/i386/initcpu.c Modified: head/lib/libc/net/rthdr.c ============================================================================== --- head/lib/libc/net/rthdr.c Wed May 29 02:03:08 2019 (r348348) +++ head/lib/libc/net/rthdr.c Wed May 29 02:08:23 2019 (r348349) @@ -282,7 +282,7 @@ inet6_rth_space(int type, int segments) return (((segments * 2) + 1) << 3); /* FALLTHROUGH */ default: - return (0); /* type not suppported */ + return (0); /* type not supported */ } } Modified: head/sys/i386/i386/initcpu.c ============================================================================== --- head/sys/i386/i386/initcpu.c Wed May 29 02:03:08 2019 (r348348) +++ head/sys/i386/i386/initcpu.c Wed May 29 02:08:23 2019 (r348349) @@ -848,7 +848,7 @@ enable_K6_wt_alloc(void) */ /* * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), - * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. + * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. * All other bits in TR12 have no effect on the processer's operation. * The I/O Trap Restart function (bit 9 of TR12) is always enabled * on the AMD-K6. @@ -898,7 +898,7 @@ enable_K6_2_wt_alloc(void) */ /* * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), - * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. + * but only the Cache Inhibit(CI) (bit 3 of TR12) is supported. * All other bits in TR12 have no effect on the processer's operation. * The I/O Trap Restart function (bit 9 of TR12) is always enabled * on the AMD-K6.