From owner-svn-src-head@FreeBSD.ORG Thu Apr 2 18:02:00 2009 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id ACA0F1065686; Thu, 2 Apr 2009 18:02:00 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 7A40D8FC0C; Thu, 2 Apr 2009 18:02:00 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id n32I20e8072207; Thu, 2 Apr 2009 18:02:00 GMT (envelope-from imp@svn.freebsd.org) Received: (from imp@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id n32I20vo072205; Thu, 2 Apr 2009 18:02:00 GMT (envelope-from imp@svn.freebsd.org) Message-Id: <200904021802.n32I20vo072205@svn.freebsd.org> From: Warner Losh Date: Thu, 2 Apr 2009 18:02:00 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r190650 - head/sys/dev/ed X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Apr 2009 18:02:03 -0000 Author: imp Date: Thu Apr 2 18:02:00 2009 New Revision: 190650 URL: http://svn.freebsd.org/changeset/base/190650 Log: Minor tweaks in the names to match the chips more closely. Modified: head/sys/dev/ed/dl100xxreg.h head/sys/dev/ed/if_ed_pccard.c Modified: head/sys/dev/ed/dl100xxreg.h ============================================================================== --- head/sys/dev/ed/dl100xxreg.h Thu Apr 2 17:58:20 2009 (r190649) +++ head/sys/dev/ed/dl100xxreg.h Thu Apr 2 18:02:00 2009 (r190650) @@ -29,15 +29,15 @@ /* Dlink chipset used on some Netgear and Dlink PCMCIA cards */ #define ED_DL100XX_MIIBUS 0x0c /* MII bus register on ASIC */ -#define ED_DL100XX_DIAG 0x0d -#define ED_DL100XX_COLLISON_DIS 4 /* Disable collision detection */ +#define ED_DL10022_DIAG 0x0d +#define ED_DL10022_COLLISON_DIS 4 /* Disable collision detection */ -#define ED_DL100XX_MII_RESET1 0x04 -#define ED_DL100XX_MII_RESET2 0x08 +#define ED_DL10022_MII_RESET1 0x04 +#define ED_DL10022_MII_RESET2 0x08 #define ED_DL100XX_MII_DATAIN 0x10 -#define ED_DL100XX_MII_DIROUT_22 0x20 -#define ED_DL100XX_MII_DIROUT_19 0x10 -#define ED_DL100XX_MII_DIROUT 0x30 +#define ED_DL10022_MII_DIROUT 0x20 +#define ED_DL10019_MII_DIROUT 0x10 +#define ED_DL100XX_MII_DIROUT (ED_DL10022_MII_DIROUT | ED_DL10019_MII_DIROUT) #define ED_DL100XX_MII_DATAOUT 0x40 #define ED_DL100XX_MII_CLK 0x80 Modified: head/sys/dev/ed/if_ed_pccard.c ============================================================================== --- head/sys/dev/ed/if_ed_pccard.c Thu Apr 2 17:58:20 2009 (r190649) +++ head/sys/dev/ed/if_ed_pccard.c Thu Apr 2 18:02:00 2009 (r190650) @@ -439,9 +439,9 @@ ed_pccard_tick(void *arg) if (mii->mii_media_status & IFM_ACTIVE && media != mii->mii_media_status && 0 && sc->chip_type == ED_CHIP_TYPE_DL10022) { - ed_asic_outb(sc, ED_DL100XX_DIAG, + ed_asic_outb(sc, ED_DL10022_DIAG, (mii->mii_media_active & IFM_FDX) ? - ED_DL100XX_COLLISON_DIS : 0); + ED_DL10022_COLLISON_DIS : 0); } } @@ -683,15 +683,15 @@ ed_pccard_dl100xx_mii_reset(struct ed_so if (sc->chip_type != ED_CHIP_TYPE_DL10022) return; - ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL100XX_MII_RESET2); + ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2); DELAY(10); ed_asic_outb(sc, ED_DL100XX_MIIBUS, - ED_DL100XX_MII_RESET2 | ED_DL100XX_MII_RESET1); + ED_DL10022_MII_RESET2 | ED_DL10022_MII_RESET1); DELAY(10); - ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL100XX_MII_RESET2); + ed_asic_outb(sc, ED_DL100XX_MIIBUS, ED_DL10022_MII_RESET2); DELAY(10); ed_asic_outb(sc, ED_DL100XX_MIIBUS, - ED_DL100XX_MII_RESET2 | ED_DL100XX_MII_RESET1); + ED_DL10022_MII_RESET2 | ED_DL10022_MII_RESET1); DELAY(10); ed_asic_outb(sc, ED_DL100XX_MIIBUS, 0); }