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Date:      Thu, 02 Aug 2001 21:57:23 -0700
From:      Terry Lambert <tlambert2@mindspring.com>
To:        mark tinguely <tinguely@web.cs.ndsu.nodak.edu>
Cc:        culverk@wam.umd.edu, riel@conectiva.com.br, craiglei@pasia.com.cn, freebsd-hackers@FreeBSD.ORG
Subject:   Re: How to visit physical memory above 4G?
Message-ID:  <3B6A2F33.88499A73@mindspring.com>
References:  <200108021414.f72EEBS78044@web.cs.ndsu.nodak.edu>

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mark tinguely wrote:
> >  Also, the PIII CAN'T natively support more than 4GB of ram. If a
> >  particular PIII motherboard supports this, then it's using some kind of
> >  wierd chipset that allows this to happen. 4GB is the limit with a 32 bit
> >  chip I believe; and the PIII is a 32-bit chip.
> 
> Since the Pentium Pro processor, the Intel chipsets support a
> physical address extension (PAE) which has 4 extra addressing
> bits, and a third level of page table indirection called the
> page-directory-pointer-table base address field.

Bit 5 of control register 4, and then it uses the top 27 bits
of control register 3 to select a 32 byte aligned region in
the lower 4G.  It also changes the PSE bit to refer to 2M
instead of 4M pages, so your would needto DISABLE_PSE, or the
FreeBSD kernel would freak when it enabled the "4M" page on
the kernel itself.

Then the high 4 bits are used to pick a pointer entry (which
is effectively a software segment register select, for all
practical purposes), giving you 64G of addressable space,
in chunks of 4G at a time.

Practically, you end up having to overlap this, which tends
to cut you down to 32G.


> The addressing use 64 bits for a memory pointer and the additional
> page indirection add to the overhead. The stickler is the MMU is
> still 32 bits. This means the PAE must segment the 64GB space into
> 4GB segments or 4 1GB segments. The OS must manage which pages are
> viewable to the process at this time.

Not only that: you reload CR3, and none of these pages are
really global, so you can't set the PG_G bit, and so you
get the full TLB shootdown on everything, so a segment switch
ends up shooting _everything_ down.


> There is a third mode of addressing using 2MB pages (simular to the
> 4MB page addressing mode for the 32 bit addressing scheme) that will
> only give a process access to 4GB of memory (not segmentable to
> a larger space, but can address physical memory located above the 4GB
> address).

Not really useful, unless you go back to a task gate, which
itself will limit you to 1024 things; with code + data, you
end up halving that to 512, minus overhead drops it to 510,
so you end up with a limitation on number of processes.  You
could do all the switching manually, but it is very, very hard.

Further, you can write off shared memory and shared libraries,
and some types of IPC (e.g. descriptor passing), unless you
want to rework everything.

IMO, the resulting kernel would be so slow as to prevent the
changes from being useful, due to their expense.

-- Terry

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