Date: Fri, 15 Jul 2005 14:42:47 +0200 From: "Constant, Benjamin" <bconstant@be.tiauto.com> To: 'Max Laier' <max@love2party.net> Cc: freebsd-pf@freebsd.org Subject: RE: ALTQ support on bge interface? Message-ID: <B6D948D84090A54ABCD88AA391DAAC8C01896462@tiasbel00ex00.be.eu.tiauto.com>
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This message is in MIME format. Since your mail reader does not understand this format, some or all of this message may not be legible. ------_=_NextPart_000_01C5893A.2C0FE739 Content-Type: text/plain Hi Max, I've just cvsup'ed' my src tree (against RELENG_5) but the patch doesn't apply correctly, here is the output: root@test:/usr/src/sys/dev/bge: patch < if_bge.c.diff Hmm... Looks like a unified diff to me... The text leading up to this was: -------------------------- |Index: if_bge.c |=================================================================== |RCS file: /usr/store/mlaier/fcvs/src/sys/dev/bge/if_bge.c,v |retrieving revision 1.72.2.13 |diff -u -r1.72.2.13 if_bge.c |--- if_bge.c 22 May 2005 03:17:49 -0000 1.72.2.13 |+++ if_bge.c 14 Jul 2005 20:30:14 -0000 -------------------------- Patching file if_bge.c using Plan A... Hunk #1 failed at 2399. Hunk #2 failed at 2999. Hunk #3 failed at 3040. Hunk #4 failed at 3056. Hunk #5 failed at 3222. Hunk #6 failed at 3249. Hunk #7 failed at 3261. 7 out of 7 hunks failed--saving rejects to if_bge.c.rej done I attached the .rej and .orig file... Thanks for the effort, it is very appreciated! Regards, Benjamin Constant > -----Original Message----- > From: Max Laier [mailto:max@love2party.net] > Sent: jeudi 14 juillet 2005 22:32 > To: freebsd-pf@freebsd.org > Cc: Florian C. Smeets; Constant, Benjamin > Subject: Re: ALTQ support on bge interface? > > On Monday 11 July 2005 13:32, Florian C. Smeets wrote: > > > As it is quite often used (e.g.: HP DL380 server), are there any > > > plan to support ALTQ on bge interface? > > > > bge has altq suppot in -CURRENT but it seems that it was > never merged > > back to RELENG_5. > > Here is a patch relative to RELENG_5. Please take it for a > spin and let me know if it works reliably. > > -- > /"\ Best regards, | mlaier@freebsd.org > \ / Max Laier | ICQ #67774661 > X http://pf4freebsd.love2party.net/ | mlaier@EFnet > / \ ASCII Ribbon Campaign | Against HTML Mail and News > The information contained in this transmission may contain privileged and confidential information. It is intended only for the use of the person(s) named above. If you are not the intended recipient, you are hereby notified that any review, dissemination, distribution or duplication of this communication is strictly prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. This communication is from TI Automotive. ------_=_NextPart_000_01C5893A.2C0FE739 Content-Type: application/octet-stream; name="if_bge.c.rej" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="if_bge.c.rej" ***************=0A= *** 2399,2405 ****=0A= ifp->if_watchdog =3D bge_watchdog; ifp->if_init =3D bge_init; ifp->if_mtu =3D ETHERMTU; - ifp->if_snd.ifq_maxlen =3D BGE_TX_RING_CNT - 1; ifp->if_hwassist =3D BGE_CSUM_FEATURES; /* NB: the code for RX csum offload is disabled for now */ ifp->if_capabilities =3D IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING | --- 2399,2407 ----=0A= ifp->if_watchdog =3D bge_watchdog; ifp->if_init =3D bge_init; ifp->if_mtu =3D ETHERMTU; + ifp->if_snd.ifq_drv_maxlen =3D BGE_TX_RING_CNT - 1; + IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); + IFQ_SET_READY(&ifp->if_snd); ifp->if_hwassist =3D BGE_CSUM_FEATURES; /* NB: the code for RX csum offload is disabled for now */ ifp->if_capabilities =3D IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING | ***************=0A= *** 2997,3003 ****=0A= /* Re-enable interrupts. */ CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); =20 - if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head !=3D NULL) bge_start_locked(ifp); =20 BGE_UNLOCK(sc); --- 2999,3005 ----=0A= /* Re-enable interrupts. */ CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); =20 + if (ifp->if_flags & IFF_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) bge_start_locked(ifp); =20 BGE_UNLOCK(sc); ***************=0A= *** 3038,3044 ****=0A= if (bootverbose) printf("bge%d: gigabit link up\n", sc->bge_unit); - if (ifp->if_snd.ifq_head !=3D NULL) bge_start_locked(ifp); } return; --- 3040,3046 ----=0A= if (bootverbose) printf("bge%d: gigabit link up\n", sc->bge_unit); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) bge_start_locked(ifp); } return; ***************=0A= *** 3054,3060 ****=0A= IFM_SUBTYPE(mii->mii_media_active) =3D=3D IFM_1000_SX) && bootverbose) printf("bge%d: gigabit link up\n", sc->bge_unit); - if (ifp->if_snd.ifq_head !=3D NULL) bge_start_locked(ifp); } =20 --- 3056,3062 ----=0A= IFM_SUBTYPE(mii->mii_media_active) =3D=3D IFM_1000_SX) && bootverbose) printf("bge%d: gigabit link up\n", sc->bge_unit); + if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) bge_start_locked(ifp); } =20 ***************=0A= *** 3220,3232 ****=0A= =20 sc =3D ifp->if_softc; =20 - if (!sc->bge_link && ifp->if_snd.ifq_len < 10) return; =20 prodidx =3D CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); =20 while(sc->bge_cdata.bge_tx_chain[prodidx] =3D=3D NULL) { - IF_DEQUEUE(&ifp->if_snd, m_head); if (m_head =3D=3D NULL) break; =20 --- 3222,3234 ----=0A= =20 sc =3D ifp->if_softc; =20 + if (!sc->bge_link && IFQ_DRV_IS_EMPTY(&ifp->if_snd)) return; =20 prodidx =3D CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); =20 while(sc->bge_cdata.bge_tx_chain[prodidx] =3D=3D NULL) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); if (m_head =3D=3D NULL) break; =20 ***************=0A= *** 3247,3253 ****=0A= m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { if ((BGE_TX_RING_CNT - sc->bge_txcnt) < m_head->m_pkthdr.csum_data + 16) { - IF_PREPEND(&ifp->if_snd, m_head); ifp->if_flags |=3D IFF_OACTIVE; break; } --- 3249,3255 ----=0A= m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { if ((BGE_TX_RING_CNT - sc->bge_txcnt) < m_head->m_pkthdr.csum_data + 16) { + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); ifp->if_flags |=3D IFF_OACTIVE; break; } ***************=0A= *** 3259,3265 ****=0A= * for the NIC to drain the ring. */ if (bge_encap(sc, m_head, &prodidx)) { - IF_PREPEND(&ifp->if_snd, m_head); ifp->if_flags |=3D IFF_OACTIVE; break; } --- 3261,3267 ----=0A= * for the NIC to drain the ring. */ if (bge_encap(sc, m_head, &prodidx)) { + IFQ_DRV_PREPEND(&ifp->if_snd, m_head); ifp->if_flags |=3D IFF_OACTIVE; break; } ------_=_NextPart_000_01C5893A.2C0FE739 Content-Type: application/octet-stream; name="if_bge.c.orig" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="if_bge.c.orig" /*-=0A= * Copyright (c) 2001 Wind River Systems=0A= * Copyright (c) 1997, 1998, 1999, 2001=0A= * Bill Paul <wpaul@windriver.com>. All rights reserved.=0A= *=0A= * Redistribution and use in source and binary forms, with or = without=0A= * modification, are permitted provided that the following = conditions=0A= * are met:=0A= * 1. Redistributions of source code must retain the above copyright=0A= * notice, this list of conditions and the following disclaimer.=0A= * 2. Redistributions in binary form must reproduce the above = copyright=0A= * notice, this list of conditions and the following disclaimer in = the=0A= * documentation and/or other materials provided with the = distribution.=0A= * 3. All advertising materials mentioning features or use of this = software=0A= * must display the following acknowledgement:=0A= * This product includes software developed by Bill Paul.=0A= * 4. Neither the name of the author nor the names of any = co-contributors=0A= * may be used to endorse or promote products derived from this = software=0A= * without specific prior written permission.=0A= *=0A= * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' = AND=0A= * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, = THE=0A= * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR = PURPOSE=0A= * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS = HEAD=0A= * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, = OR=0A= * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT = OF=0A= * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR = BUSINESS=0A= * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER = IN=0A= * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR = OTHERWISE)=0A= * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED = OF=0A= * THE POSSIBILITY OF SUCH DAMAGE.=0A= */=0A= =0A= #include <sys/cdefs.h>=0A= __FBSDID("$FreeBSD: src/sys/dev/bge/if_bge.c,v 1.72.2.13 2005/05/22 = 03:17:49 silby Exp $");=0A= =0A= /*=0A= * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.=0A= *=0A= * The Broadcom BCM5700 is based on technology originally developed = by=0A= * Alteon Networks as part of the Tigon I and Tigon II gigabit = ethernet=0A= * MAC chips. The BCM5700, sometimes refered to as the Tigon III, = has=0A= * two on-board MIPS R4000 CPUs and can have as much as 16MB of = external=0A= * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, = jumbo=0A= * frames, highly configurable RX filtering, and 16 RX and TX queues=0A= * (which, along with RX filter rules, can be used for QOS = applications).=0A= * Other features, such as TCP segmentation, may be available as = part=0A= * of value-added firmware updates. Unlike the Tigon I and Tigon II,=0A= * firmware images can be stored in hardware and need not be = compiled=0A= * into the driver.=0A= *=0A= * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and = will=0A= * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.=0A= *=0A= * The BCM5701 is a single-chip solution incorporating both the = BCM5700=0A= * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the = BCM5701=0A= * does not support external SSRAM.=0A= *=0A= * Broadcom also produces a variation of the BCM5700 under the = "Altima"=0A= * brand name, which is functionally similar but lacks PCI-X = support.=0A= *=0A= * Without external SSRAM, you can only have at most 4 TX rings,=0A= * and the use of the mini RX ring is disabled. This seems to imply=0A= * that these features are simply not available on the BCM5701. As a=0A= * result, this driver does not implement any support for the mini = RX=0A= * ring.=0A= */=0A= =0A= #include <sys/param.h>=0A= #include <sys/endian.h>=0A= #include <sys/systm.h>=0A= #include <sys/sockio.h>=0A= #include <sys/mbuf.h>=0A= #include <sys/malloc.h>=0A= #include <sys/kernel.h>=0A= #include <sys/module.h>=0A= #include <sys/socket.h>=0A= #include <sys/queue.h>=0A= =0A= #include <net/if.h>=0A= #include <net/if_arp.h>=0A= #include <net/ethernet.h>=0A= #include <net/if_dl.h>=0A= #include <net/if_media.h>=0A= =0A= #include <net/bpf.h>=0A= =0A= #include <net/if_types.h>=0A= #include <net/if_vlan_var.h>=0A= =0A= #include <netinet/in_systm.h>=0A= #include <netinet/in.h>=0A= #include <netinet/ip.h>=0A= =0A= #include <machine/clock.h> /* for DELAY */=0A= #include <machine/bus_memio.h>=0A= #include <machine/bus.h>=0A= #include <machine/resource.h>=0A= #include <sys/bus.h>=0A= #include <sys/rman.h>=0A= =0A= #include <dev/mii/mii.h>=0A= #include <dev/mii/miivar.h>=0A= #include "miidevs.h"=0A= #include <dev/mii/brgphyreg.h>=0A= =0A= #include <dev/pci/pcireg.h>=0A= #include <dev/pci/pcivar.h>=0A= =0A= #include <dev/bge/if_bgereg.h>=0A= =0A= #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)=0A= =0A= MODULE_DEPEND(bge, pci, 1, 1, 1);=0A= MODULE_DEPEND(bge, ether, 1, 1, 1);=0A= MODULE_DEPEND(bge, miibus, 1, 1, 1);=0A= =0A= /* "controller miibus0" required. See GENERIC if you get errors here. = */=0A= #include "miibus_if.h"=0A= =0A= /*=0A= * Various supported device vendors/types and their names. Note: the=0A= * spec seems to indicate that the hardware still has Alteon's = vendor=0A= * ID burned into it, though it will always be overriden by the = vendor=0A= * ID in the EEPROM. Just to be safe, we cover all possibilities.=0A= */=0A= #define BGE_DEVDESC_MAX 64 /* Maximum device description length */=0A= =0A= static struct bge_type bge_devs[] =3D {=0A= { ALT_VENDORID, ALT_DEVICEID_BCM5700,=0A= "Broadcom BCM5700 Gigabit Ethernet" },=0A= { ALT_VENDORID, ALT_DEVICEID_BCM5701,=0A= "Broadcom BCM5701 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5700,=0A= "Broadcom BCM5700 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5701,=0A= "Broadcom BCM5701 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5702,=0A= "Broadcom BCM5702 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X,=0A= "Broadcom BCM5702X Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5703,=0A= "Broadcom BCM5703 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X,=0A= "Broadcom BCM5703X Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C,=0A= "Broadcom BCM5704C Dual Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S,=0A= "Broadcom BCM5704S Dual Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5705,=0A= "Broadcom BCM5705 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K,=0A= "Broadcom BCM5705K Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M,=0A= "Broadcom BCM5705M Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT,=0A= "Broadcom BCM5705M Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C,=0A= "Broadcom BCM5714C Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5721,=0A= "Broadcom BCM5721 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5750,=0A= "Broadcom BCM5750 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M,=0A= "Broadcom BCM5750M Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5751,=0A= "Broadcom BCM5751 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M,=0A= "Broadcom BCM5751M Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5782,=0A= "Broadcom BCM5782 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5788,=0A= "Broadcom BCM5788 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5789,=0A= "Broadcom BCM5789 Gigabit Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5901,=0A= "Broadcom BCM5901 Fast Ethernet" },=0A= { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2,=0A= "Broadcom BCM5901A2 Fast Ethernet" },=0A= { SK_VENDORID, SK_DEVICEID_ALTIMA,=0A= "SysKonnect Gigabit Ethernet" },=0A= { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000,=0A= "Altima AC1000 Gigabit Ethernet" },=0A= { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002,=0A= "Altima AC1002 Gigabit Ethernet" },=0A= { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100,=0A= "Altima AC9100 Gigabit Ethernet" },=0A= { 0, 0, NULL }=0A= };=0A= =0A= static int bge_probe (device_t);=0A= static int bge_attach (device_t);=0A= static int bge_detach (device_t);=0A= static void bge_release_resources=0A= (struct bge_softc *);=0A= static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, = int);=0A= static void bge_dma_map_tx_desc (void *, bus_dma_segment_t *, int,=0A= bus_size_t, int);=0A= static int bge_dma_alloc (device_t);=0A= static void bge_dma_free (struct bge_softc *);=0A= =0A= static void bge_txeof (struct bge_softc *);=0A= static void bge_rxeof (struct bge_softc *);=0A= =0A= static void bge_tick_locked (struct bge_softc *);=0A= static void bge_tick (void *);=0A= static void bge_stats_update (struct bge_softc *);=0A= static void bge_stats_update_regs=0A= (struct bge_softc *);=0A= static int bge_encap (struct bge_softc *, struct mbuf *,=0A= u_int32_t *);=0A= =0A= static void bge_intr (void *);=0A= static void bge_start_locked (struct ifnet *);=0A= static void bge_start (struct ifnet *);=0A= static int bge_ioctl (struct ifnet *, u_long, caddr_t);=0A= static void bge_init_locked (struct bge_softc *);=0A= static void bge_init (void *);=0A= static void bge_stop (struct bge_softc *);=0A= static void bge_watchdog (struct ifnet *);=0A= static void bge_shutdown (device_t);=0A= static int bge_ifmedia_upd (struct ifnet *);=0A= static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *);=0A= =0A= static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t = *);=0A= static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int);=0A= =0A= static void bge_setmulti (struct bge_softc *);=0A= =0A= static void bge_handle_events (struct bge_softc *);=0A= static int bge_alloc_jumbo_mem (struct bge_softc *);=0A= static void bge_free_jumbo_mem (struct bge_softc *);=0A= static void *bge_jalloc (struct bge_softc *);=0A= static void bge_jfree (void *, void *);=0A= static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *);=0A= static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf = *);=0A= static int bge_init_rx_ring_std (struct bge_softc *);=0A= static void bge_free_rx_ring_std (struct bge_softc *);=0A= static int bge_init_rx_ring_jumbo (struct bge_softc *);=0A= static void bge_free_rx_ring_jumbo (struct bge_softc *);=0A= static void bge_free_tx_ring (struct bge_softc *);=0A= static int bge_init_tx_ring (struct bge_softc *);=0A= =0A= static int bge_chipinit (struct bge_softc *);=0A= static int bge_blockinit (struct bge_softc *);=0A= =0A= #ifdef notdef=0A= static u_int8_t bge_vpd_readbyte(struct bge_softc *, int);=0A= static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, = int);=0A= static void bge_vpd_read (struct bge_softc *);=0A= #endif=0A= =0A= static u_int32_t bge_readmem_ind=0A= (struct bge_softc *, int);=0A= static void bge_writemem_ind (struct bge_softc *, int, int);=0A= #ifdef notdef=0A= static u_int32_t bge_readreg_ind=0A= (struct bge_softc *, int);=0A= #endif=0A= static void bge_writereg_ind (struct bge_softc *, int, int);=0A= =0A= static int bge_miibus_readreg (device_t, int, int);=0A= static int bge_miibus_writereg (device_t, int, int, int);=0A= static void bge_miibus_statchg (device_t);=0A= =0A= static void bge_reset (struct bge_softc *);=0A= =0A= static device_method_t bge_methods[] =3D {=0A= /* Device interface */=0A= DEVMETHOD(device_probe, bge_probe),=0A= DEVMETHOD(device_attach, bge_attach),=0A= DEVMETHOD(device_detach, bge_detach),=0A= DEVMETHOD(device_shutdown, bge_shutdown),=0A= =0A= /* bus interface */=0A= DEVMETHOD(bus_print_child, bus_generic_print_child),=0A= DEVMETHOD(bus_driver_added, bus_generic_driver_added),=0A= =0A= /* MII interface */=0A= DEVMETHOD(miibus_readreg, bge_miibus_readreg),=0A= DEVMETHOD(miibus_writereg, bge_miibus_writereg),=0A= DEVMETHOD(miibus_statchg, bge_miibus_statchg),=0A= =0A= { 0, 0 }=0A= };=0A= =0A= static driver_t bge_driver =3D {=0A= "bge",=0A= bge_methods,=0A= sizeof(struct bge_softc)=0A= };=0A= =0A= static devclass_t bge_devclass;=0A= =0A= DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);=0A= DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);=0A= =0A= static u_int32_t=0A= bge_readmem_ind(sc, off)=0A= struct bge_softc *sc;=0A= int off;=0A= {=0A= device_t dev;=0A= =0A= dev =3D sc->bge_dev;=0A= =0A= pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);=0A= return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));=0A= }=0A= =0A= static void=0A= bge_writemem_ind(sc, off, val)=0A= struct bge_softc *sc;=0A= int off, val;=0A= {=0A= device_t dev;=0A= =0A= dev =3D sc->bge_dev;=0A= =0A= pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);=0A= pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);=0A= =0A= return;=0A= }=0A= =0A= #ifdef notdef=0A= static u_int32_t=0A= bge_readreg_ind(sc, off)=0A= struct bge_softc *sc;=0A= int off;=0A= {=0A= device_t dev;=0A= =0A= dev =3D sc->bge_dev;=0A= =0A= pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);=0A= return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));=0A= }=0A= #endif=0A= =0A= static void=0A= bge_writereg_ind(sc, off, val)=0A= struct bge_softc *sc;=0A= int off, val;=0A= {=0A= device_t dev;=0A= =0A= dev =3D sc->bge_dev;=0A= =0A= pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);=0A= pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Map a single buffer address.=0A= */=0A= =0A= static void=0A= bge_dma_map_addr(arg, segs, nseg, error)=0A= void *arg;=0A= bus_dma_segment_t *segs;=0A= int nseg;=0A= int error;=0A= {=0A= struct bge_dmamap_arg *ctx;=0A= =0A= if (error)=0A= return;=0A= =0A= ctx =3D arg;=0A= =0A= if (nseg > ctx->bge_maxsegs) {=0A= ctx->bge_maxsegs =3D 0;=0A= return;=0A= }=0A= =0A= ctx->bge_busaddr =3D segs->ds_addr;=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Map an mbuf chain into an TX ring.=0A= */=0A= =0A= static void=0A= bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error)=0A= void *arg;=0A= bus_dma_segment_t *segs;=0A= int nseg;=0A= bus_size_t mapsize;=0A= int error;=0A= {=0A= struct bge_dmamap_arg *ctx;=0A= struct bge_tx_bd *d =3D NULL;=0A= int i =3D 0, idx;=0A= =0A= if (error)=0A= return;=0A= =0A= ctx =3D arg;=0A= =0A= /* Signal error to caller if there's too many segments */=0A= if (nseg > ctx->bge_maxsegs) {=0A= ctx->bge_maxsegs =3D 0;=0A= return;=0A= }=0A= =0A= idx =3D ctx->bge_idx;=0A= while(1) {=0A= d =3D &ctx->bge_ring[idx];=0A= d->bge_addr.bge_addr_lo =3D=0A= htole32(BGE_ADDR_LO(segs[i].ds_addr));=0A= d->bge_addr.bge_addr_hi =3D=0A= htole32(BGE_ADDR_HI(segs[i].ds_addr));=0A= d->bge_len =3D htole16(segs[i].ds_len);=0A= d->bge_flags =3D htole16(ctx->bge_flags);=0A= i++;=0A= if (i =3D=3D nseg)=0A= break;=0A= BGE_INC(idx, BGE_TX_RING_CNT);=0A= }=0A= =0A= d->bge_flags |=3D htole16(BGE_TXBDFLAG_END);=0A= ctx->bge_maxsegs =3D nseg;=0A= ctx->bge_idx =3D idx;=0A= =0A= return;=0A= }=0A= =0A= =0A= #ifdef notdef=0A= static u_int8_t=0A= bge_vpd_readbyte(sc, addr)=0A= struct bge_softc *sc;=0A= int addr;=0A= {=0A= int i;=0A= device_t dev;=0A= u_int32_t val;=0A= =0A= dev =3D sc->bge_dev;=0A= pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);=0A= for (i =3D 0; i < BGE_TIMEOUT * 10; i++) {=0A= DELAY(10);=0A= if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)=0A= break;=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: VPD read timed out\n", sc->bge_unit);=0A= return(0);=0A= }=0A= =0A= val =3D pci_read_config(dev, BGE_PCI_VPD_DATA, 4);=0A= =0A= return((val >> ((addr % 4) * 8)) & 0xFF);=0A= }=0A= =0A= static void=0A= bge_vpd_read_res(sc, res, addr)=0A= struct bge_softc *sc;=0A= struct vpd_res *res;=0A= int addr;=0A= {=0A= int i;=0A= u_int8_t *ptr;=0A= =0A= ptr =3D (u_int8_t *)res;=0A= for (i =3D 0; i < sizeof(struct vpd_res); i++)=0A= ptr[i] =3D bge_vpd_readbyte(sc, i + addr);=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_vpd_read(sc)=0A= struct bge_softc *sc;=0A= {=0A= int pos =3D 0, i;=0A= struct vpd_res res;=0A= =0A= if (sc->bge_vpd_prodname !=3D NULL)=0A= free(sc->bge_vpd_prodname, M_DEVBUF);=0A= if (sc->bge_vpd_readonly !=3D NULL)=0A= free(sc->bge_vpd_readonly, M_DEVBUF);=0A= sc->bge_vpd_prodname =3D NULL;=0A= sc->bge_vpd_readonly =3D NULL;=0A= =0A= bge_vpd_read_res(sc, &res, pos);=0A= =0A= if (res.vr_id !=3D VPD_RES_ID) {=0A= printf("bge%d: bad VPD resource id: expected %x got %x\n",=0A= sc->bge_unit, VPD_RES_ID, res.vr_id);=0A= return;=0A= }=0A= =0A= pos +=3D sizeof(res);=0A= sc->bge_vpd_prodname =3D malloc(res.vr_len + 1, M_DEVBUF, = M_NOWAIT);=0A= for (i =3D 0; i < res.vr_len; i++)=0A= sc->bge_vpd_prodname[i] =3D bge_vpd_readbyte(sc, i + pos);=0A= sc->bge_vpd_prodname[i] =3D '\0';=0A= pos +=3D i;=0A= =0A= bge_vpd_read_res(sc, &res, pos);=0A= =0A= if (res.vr_id !=3D VPD_RES_READ) {=0A= printf("bge%d: bad VPD resource id: expected %x got %x\n",=0A= sc->bge_unit, VPD_RES_READ, res.vr_id);=0A= return;=0A= }=0A= =0A= pos +=3D sizeof(res);=0A= sc->bge_vpd_readonly =3D malloc(res.vr_len, M_DEVBUF, M_NOWAIT);=0A= for (i =3D 0; i < res.vr_len + 1; i++)=0A= sc->bge_vpd_readonly[i] =3D bge_vpd_readbyte(sc, i + pos);=0A= =0A= return;=0A= }=0A= #endif=0A= =0A= /*=0A= * Read a byte of data stored in the EEPROM at address 'addr.' The=0A= * BCM570x supports both the traditional bitbang interface and an=0A= * auto access interface for reading the EEPROM. We use the auto=0A= * access method.=0A= */=0A= static u_int8_t=0A= bge_eeprom_getbyte(sc, addr, dest)=0A= struct bge_softc *sc;=0A= int addr;=0A= u_int8_t *dest;=0A= {=0A= int i;=0A= u_int32_t byte =3D 0;=0A= =0A= /*=0A= * Enable use of auto EEPROM access so we can avoid=0A= * having to use the bitbang method.=0A= */=0A= BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);=0A= =0A= /* Reset the EEPROM, load the clock period. */=0A= CSR_WRITE_4(sc, BGE_EE_ADDR,=0A= BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));=0A= DELAY(20);=0A= =0A= /* Issue the read EEPROM command. */=0A= CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);=0A= =0A= /* Wait for completion */=0A= for(i =3D 0; i < BGE_TIMEOUT * 10; i++) {=0A= DELAY(10);=0A= if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)=0A= break;=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: eeprom read timed out\n", sc->bge_unit);=0A= return(0);=0A= }=0A= =0A= /* Get result. */=0A= byte =3D CSR_READ_4(sc, BGE_EE_DATA);=0A= =0A= *dest =3D (byte >> ((addr % 4) * 8)) & 0xFF;=0A= =0A= return(0);=0A= }=0A= =0A= /*=0A= * Read a sequence of bytes from the EEPROM.=0A= */=0A= static int=0A= bge_read_eeprom(sc, dest, off, cnt)=0A= struct bge_softc *sc;=0A= caddr_t dest;=0A= int off;=0A= int cnt;=0A= {=0A= int err =3D 0, i;=0A= u_int8_t byte =3D 0;=0A= =0A= for (i =3D 0; i < cnt; i++) {=0A= err =3D bge_eeprom_getbyte(sc, off + i, &byte);=0A= if (err)=0A= break;=0A= *(dest + i) =3D byte;=0A= }=0A= =0A= return(err ? 1 : 0);=0A= }=0A= =0A= static int=0A= bge_miibus_readreg(dev, phy, reg)=0A= device_t dev;=0A= int phy, reg;=0A= {=0A= struct bge_softc *sc;=0A= u_int32_t val, autopoll;=0A= int i;=0A= =0A= sc =3D device_get_softc(dev);=0A= =0A= /*=0A= * Broadcom's own driver always assumes the internal=0A= * PHY is at GMII address 1. On some chips, the PHY responds=0A= * to accesses at all addresses, which could cause us to=0A= * bogusly attach the PHY 32 times at probe type. Always=0A= * restricting the lookup to address 1 is simpler than=0A= * trying to figure out which chips revisions should be=0A= * special-cased.=0A= */=0A= if (phy !=3D 1)=0A= return(0);=0A= =0A= /* Reading with autopolling on may trigger PCI errors */=0A= autopoll =3D CSR_READ_4(sc, BGE_MI_MODE);=0A= if (autopoll & BGE_MIMODE_AUTOPOLL) {=0A= BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);=0A= DELAY(40);=0A= }=0A= =0A= CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|=0A= BGE_MIPHY(phy)|BGE_MIREG(reg));=0A= =0A= for (i =3D 0; i < BGE_TIMEOUT; i++) {=0A= val =3D CSR_READ_4(sc, BGE_MI_COMM);=0A= if (!(val & BGE_MICOMM_BUSY))=0A= break;=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: PHY read timed out\n", sc->bge_unit);=0A= val =3D 0;=0A= goto done;=0A= }=0A= =0A= val =3D CSR_READ_4(sc, BGE_MI_COMM);=0A= =0A= done:=0A= if (autopoll & BGE_MIMODE_AUTOPOLL) {=0A= BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);=0A= DELAY(40);=0A= }=0A= =0A= if (val & BGE_MICOMM_READFAIL)=0A= return(0);=0A= =0A= return(val & 0xFFFF);=0A= }=0A= =0A= static int=0A= bge_miibus_writereg(dev, phy, reg, val)=0A= device_t dev;=0A= int phy, reg, val;=0A= {=0A= struct bge_softc *sc;=0A= u_int32_t autopoll;=0A= int i;=0A= =0A= sc =3D device_get_softc(dev);=0A= =0A= /* Reading with autopolling on may trigger PCI errors */=0A= autopoll =3D CSR_READ_4(sc, BGE_MI_MODE);=0A= if (autopoll & BGE_MIMODE_AUTOPOLL) {=0A= BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);=0A= DELAY(40);=0A= }=0A= =0A= CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|=0A= BGE_MIPHY(phy)|BGE_MIREG(reg)|val);=0A= =0A= for (i =3D 0; i < BGE_TIMEOUT; i++) {=0A= if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))=0A= break;=0A= }=0A= =0A= if (autopoll & BGE_MIMODE_AUTOPOLL) {=0A= BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);=0A= DELAY(40);=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: PHY read timed out\n", sc->bge_unit);=0A= return(0);=0A= }=0A= =0A= return(0);=0A= }=0A= =0A= static void=0A= bge_miibus_statchg(dev)=0A= device_t dev;=0A= {=0A= struct bge_softc *sc;=0A= struct mii_data *mii;=0A= =0A= sc =3D device_get_softc(dev);=0A= mii =3D device_get_softc(sc->bge_miibus);=0A= =0A= BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);=0A= if (IFM_SUBTYPE(mii->mii_media_active) =3D=3D IFM_1000_T) {=0A= BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);=0A= } else {=0A= BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);=0A= }=0A= =0A= if ((mii->mii_media_active & IFM_GMASK) =3D=3D IFM_FDX) {=0A= BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);=0A= } else {=0A= BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);=0A= }=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Handle events that have triggered interrupts.=0A= */=0A= static void=0A= bge_handle_events(sc)=0A= struct bge_softc *sc;=0A= {=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Memory management for jumbo frames.=0A= */=0A= =0A= static int=0A= bge_alloc_jumbo_mem(sc)=0A= struct bge_softc *sc;=0A= {=0A= caddr_t ptr;=0A= register int i, error;=0A= struct bge_jpool_entry *entry;=0A= =0A= /* Create tag for jumbo buffer block */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL,=0A= &sc->bge_cdata.bge_jumbo_tag);=0A= =0A= if (error) {=0A= printf("bge%d: could not allocate jumbo dma tag\n",=0A= sc->bge_unit);=0A= return (ENOMEM);=0A= }=0A= =0A= /* Allocate DMA'able memory for jumbo buffer block */=0A= =0A= error =3D bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag,=0A= (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT,=0A= &sc->bge_cdata.bge_jumbo_map);=0A= =0A= if (error)=0A= return (ENOMEM);=0A= =0A= SLIST_INIT(&sc->bge_jfree_listhead);=0A= SLIST_INIT(&sc->bge_jinuse_listhead);=0A= =0A= /*=0A= * Now divide it up into 9K pieces and save the addresses=0A= * in an array.=0A= */=0A= ptr =3D sc->bge_ldata.bge_jumbo_buf;=0A= for (i =3D 0; i < BGE_JSLOTS; i++) {=0A= sc->bge_cdata.bge_jslots[i] =3D ptr;=0A= ptr +=3D BGE_JLEN;=0A= entry =3D malloc(sizeof(struct bge_jpool_entry),=0A= M_DEVBUF, M_NOWAIT);=0A= if (entry =3D=3D NULL) {=0A= bge_free_jumbo_mem(sc);=0A= sc->bge_ldata.bge_jumbo_buf =3D NULL;=0A= printf("bge%d: no memory for jumbo "=0A= "buffer queue!\n", sc->bge_unit);=0A= return(ENOBUFS);=0A= }=0A= entry->slot =3D i;=0A= SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,=0A= entry, jpool_entries);=0A= }=0A= =0A= return(0);=0A= }=0A= =0A= static void=0A= bge_free_jumbo_mem(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= struct bge_jpool_entry *entry;=0A= =0A= for (i =3D 0; i < BGE_JSLOTS; i++) {=0A= entry =3D SLIST_FIRST(&sc->bge_jfree_listhead);=0A= SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);=0A= free(entry, M_DEVBUF);=0A= }=0A= =0A= /* Destroy jumbo buffer block */=0A= =0A= if (sc->bge_ldata.bge_rx_jumbo_ring)=0A= bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag,=0A= sc->bge_ldata.bge_jumbo_buf,=0A= sc->bge_cdata.bge_jumbo_map);=0A= =0A= if (sc->bge_cdata.bge_rx_jumbo_ring_map)=0A= bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag,=0A= sc->bge_cdata.bge_jumbo_map);=0A= =0A= if (sc->bge_cdata.bge_jumbo_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag);=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Allocate a jumbo buffer.=0A= */=0A= static void *=0A= bge_jalloc(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct bge_jpool_entry *entry;=0A= =0A= entry =3D SLIST_FIRST(&sc->bge_jfree_listhead);=0A= =0A= if (entry =3D=3D NULL) {=0A= printf("bge%d: no free jumbo buffers\n", sc->bge_unit);=0A= return(NULL);=0A= }=0A= =0A= SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries);=0A= SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries);=0A= return(sc->bge_cdata.bge_jslots[entry->slot]);=0A= }=0A= =0A= /*=0A= * Release a jumbo buffer.=0A= */=0A= static void=0A= bge_jfree(buf, args)=0A= void *buf;=0A= void *args;=0A= {=0A= struct bge_jpool_entry *entry;=0A= struct bge_softc *sc;=0A= int i;=0A= =0A= /* Extract the softc struct pointer. */=0A= sc =3D (struct bge_softc *)args;=0A= =0A= if (sc =3D=3D NULL)=0A= panic("bge_jfree: can't find softc pointer!");=0A= =0A= /* calculate the slot this buffer belongs to */=0A= =0A= i =3D ((vm_offset_t)buf=0A= - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN;=0A= =0A= if ((i < 0) || (i >=3D BGE_JSLOTS))=0A= panic("bge_jfree: asked to free buffer that we don't manage!");=0A= =0A= entry =3D SLIST_FIRST(&sc->bge_jinuse_listhead);=0A= if (entry =3D=3D NULL)=0A= panic("bge_jfree: buffer not in use!");=0A= entry->slot =3D i;=0A= SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries);=0A= SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries);=0A= =0A= return;=0A= }=0A= =0A= =0A= /*=0A= * Intialize a standard receive ring descriptor.=0A= */=0A= static int=0A= bge_newbuf_std(sc, i, m)=0A= struct bge_softc *sc;=0A= int i;=0A= struct mbuf *m;=0A= {=0A= struct mbuf *m_new =3D NULL;=0A= struct bge_rx_bd *r;=0A= struct bge_dmamap_arg ctx;=0A= int error;=0A= =0A= if (m =3D=3D NULL) {=0A= MGETHDR(m_new, M_DONTWAIT, MT_DATA);=0A= if (m_new =3D=3D NULL) {=0A= return(ENOBUFS);=0A= }=0A= =0A= MCLGET(m_new, M_DONTWAIT);=0A= if (!(m_new->m_flags & M_EXT)) {=0A= m_freem(m_new);=0A= return(ENOBUFS);=0A= }=0A= m_new->m_len =3D m_new->m_pkthdr.len =3D MCLBYTES;=0A= } else {=0A= m_new =3D m;=0A= m_new->m_len =3D m_new->m_pkthdr.len =3D MCLBYTES;=0A= m_new->m_data =3D m_new->m_ext.ext_buf;=0A= }=0A= =0A= if (!sc->bge_rx_alignment_bug)=0A= m_adj(m_new, ETHER_ALIGN);=0A= sc->bge_cdata.bge_rx_std_chain[i] =3D m_new;=0A= r =3D &sc->bge_ldata.bge_rx_std_ring[i];=0A= ctx.bge_maxsegs =3D 1;=0A= ctx.sc =3D sc;=0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *),=0A= m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= if (error || ctx.bge_maxsegs =3D=3D 0) {=0A= if (m =3D=3D NULL)=0A= m_freem(m_new);=0A= return(ENOMEM);=0A= }=0A= r->bge_addr.bge_addr_lo =3D htole32(BGE_ADDR_LO(ctx.bge_busaddr));=0A= r->bge_addr.bge_addr_hi =3D htole32(BGE_ADDR_HI(ctx.bge_busaddr));=0A= r->bge_flags =3D htole16(BGE_RXBDFLAG_END);=0A= r->bge_len =3D htole16(m_new->m_len);=0A= r->bge_idx =3D htole16(i);=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_rx_std_dmamap[i],=0A= BUS_DMASYNC_PREREAD);=0A= =0A= return(0);=0A= }=0A= =0A= /*=0A= * Initialize a jumbo receive ring descriptor. This allocates=0A= * a jumbo buffer from the pool managed internally by the driver.=0A= */=0A= static int=0A= bge_newbuf_jumbo(sc, i, m)=0A= struct bge_softc *sc;=0A= int i;=0A= struct mbuf *m;=0A= {=0A= struct mbuf *m_new =3D NULL;=0A= struct bge_rx_bd *r;=0A= struct bge_dmamap_arg ctx;=0A= int error;=0A= =0A= if (m =3D=3D NULL) {=0A= caddr_t *buf =3D NULL;=0A= =0A= /* Allocate the mbuf. */=0A= MGETHDR(m_new, M_DONTWAIT, MT_DATA);=0A= if (m_new =3D=3D NULL) {=0A= return(ENOBUFS);=0A= }=0A= =0A= /* Allocate the jumbo buffer */=0A= buf =3D bge_jalloc(sc);=0A= if (buf =3D=3D NULL) {=0A= m_freem(m_new);=0A= printf("bge%d: jumbo allocation failed "=0A= "-- packet dropped!\n", sc->bge_unit);=0A= return(ENOBUFS);=0A= }=0A= =0A= /* Attach the buffer to the mbuf. */=0A= m_new->m_data =3D (void *) buf;=0A= m_new->m_len =3D m_new->m_pkthdr.len =3D BGE_JUMBO_FRAMELEN;=0A= MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree,=0A= (struct bge_softc *)sc, 0, EXT_NET_DRV);=0A= } else {=0A= m_new =3D m;=0A= m_new->m_data =3D m_new->m_ext.ext_buf;=0A= m_new->m_ext.ext_size =3D BGE_JUMBO_FRAMELEN;=0A= }=0A= =0A= if (!sc->bge_rx_alignment_bug)=0A= m_adj(m_new, ETHER_ALIGN);=0A= /* Set up the descriptor. */=0A= sc->bge_cdata.bge_rx_jumbo_chain[i] =3D m_new;=0A= r =3D &sc->bge_ldata.bge_rx_jumbo_ring[i];=0A= ctx.bge_maxsegs =3D 1;=0A= ctx.sc =3D sc;=0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo,=0A= sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *),=0A= m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= if (error || ctx.bge_maxsegs =3D=3D 0) {=0A= if (m =3D=3D NULL)=0A= m_freem(m_new);=0A= return(ENOMEM);=0A= }=0A= r->bge_addr.bge_addr_lo =3D htole32(BGE_ADDR_LO(ctx.bge_busaddr));=0A= r->bge_addr.bge_addr_hi =3D htole32(BGE_ADDR_HI(ctx.bge_busaddr));=0A= r->bge_flags =3D htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING);=0A= r->bge_len =3D htole16(m_new->m_len);=0A= r->bge_idx =3D htole16(i);=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_rx_jumbo_dmamap[i],=0A= BUS_DMASYNC_PREREAD);=0A= =0A= return(0);=0A= }=0A= =0A= /*=0A= * The standard receive ring has 512 entries in it. At 2K per mbuf = cluster,=0A= * that's 1MB or memory, which is a lot. For now, we fill only the = first=0A= * 256 ring entries and hope that our CPU is fast enough to keep up = with=0A= * the NIC.=0A= */=0A= static int=0A= bge_init_rx_ring_std(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= =0A= for (i =3D 0; i < BGE_SSLOTS; i++) {=0A= if (bge_newbuf_std(sc, i, NULL) =3D=3D ENOBUFS)=0A= return(ENOBUFS);=0A= };=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_cdata.bge_rx_std_ring_map,=0A= BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);=0A= =0A= sc->bge_std =3D i - 1;=0A= CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);=0A= =0A= return(0);=0A= }=0A= =0A= static void=0A= bge_free_rx_ring_std(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= =0A= for (i =3D 0; i < BGE_STD_RX_RING_CNT; i++) {=0A= if (sc->bge_cdata.bge_rx_std_chain[i] !=3D NULL) {=0A= m_freem(sc->bge_cdata.bge_rx_std_chain[i]);=0A= sc->bge_cdata.bge_rx_std_chain[i] =3D NULL;=0A= bus_dmamap_unload(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_rx_std_dmamap[i]);=0A= }=0A= bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],=0A= sizeof(struct bge_rx_bd));=0A= }=0A= =0A= return;=0A= }=0A= =0A= static int=0A= bge_init_rx_ring_jumbo(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= struct bge_rcb *rcb;=0A= =0A= for (i =3D 0; i < BGE_JUMBO_RX_RING_CNT; i++) {=0A= if (bge_newbuf_jumbo(sc, i, NULL) =3D=3D ENOBUFS)=0A= return(ENOBUFS);=0A= };=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map,=0A= BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);=0A= =0A= sc->bge_jumbo =3D i - 1;=0A= =0A= rcb =3D &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;=0A= rcb->bge_maxlen_flags =3D BGE_RCB_MAXLEN_FLAGS(0, 0);=0A= CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, = rcb->bge_maxlen_flags);=0A= =0A= CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);=0A= =0A= return(0);=0A= }=0A= =0A= static void=0A= bge_free_rx_ring_jumbo(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= =0A= for (i =3D 0; i < BGE_JUMBO_RX_RING_CNT; i++) {=0A= if (sc->bge_cdata.bge_rx_jumbo_chain[i] !=3D NULL) {=0A= m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);=0A= sc->bge_cdata.bge_rx_jumbo_chain[i] =3D NULL;=0A= bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,=0A= sc->bge_cdata.bge_rx_jumbo_dmamap[i]);=0A= }=0A= bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],=0A= sizeof(struct bge_rx_bd));=0A= }=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_free_tx_ring(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= =0A= if (sc->bge_ldata.bge_tx_ring =3D=3D NULL)=0A= return;=0A= =0A= for (i =3D 0; i < BGE_TX_RING_CNT; i++) {=0A= if (sc->bge_cdata.bge_tx_chain[i] !=3D NULL) {=0A= m_freem(sc->bge_cdata.bge_tx_chain[i]);=0A= sc->bge_cdata.bge_tx_chain[i] =3D NULL;=0A= bus_dmamap_unload(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_tx_dmamap[i]);=0A= }=0A= bzero((char *)&sc->bge_ldata.bge_tx_ring[i],=0A= sizeof(struct bge_tx_bd));=0A= }=0A= =0A= return;=0A= }=0A= =0A= static int=0A= bge_init_tx_ring(sc)=0A= struct bge_softc *sc;=0A= {=0A= sc->bge_txcnt =3D 0;=0A= sc->bge_tx_saved_considx =3D 0;=0A= =0A= CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);=0A= /* 5700 b2 errata */=0A= if (sc->bge_chiprev =3D=3D BGE_CHIPREV_5700_BX)=0A= CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);=0A= =0A= CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);=0A= /* 5700 b2 errata */=0A= if (sc->bge_chiprev =3D=3D BGE_CHIPREV_5700_BX)=0A= CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);=0A= =0A= return(0);=0A= }=0A= =0A= static void=0A= bge_setmulti(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct ifnet *ifp;=0A= struct ifmultiaddr *ifma;=0A= u_int32_t hashes[4] =3D { 0, 0, 0, 0 };=0A= int h, i;=0A= =0A= BGE_LOCK_ASSERT(sc);=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {=0A= for (i =3D 0; i < 4; i++)=0A= CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);=0A= return;=0A= }=0A= =0A= /* First, zot all the existing filters. */=0A= for (i =3D 0; i < 4; i++)=0A= CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);=0A= =0A= /* Now program new ones. */=0A= TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {=0A= if (ifma->ifma_addr->sa_family !=3D AF_LINK)=0A= continue;=0A= h =3D ether_crc32_le(LLADDR((struct sockaddr_dl *)=0A= ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F;=0A= hashes[(h & 0x60) >> 5] |=3D 1 << (h & 0x1F);=0A= }=0A= =0A= for (i =3D 0; i < 4; i++)=0A= CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Do endian, PCI and DMA initialization. Also check the on-board = ROM=0A= * self-test results.=0A= */=0A= static int=0A= bge_chipinit(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= u_int32_t dma_rw_ctl;=0A= =0A= /* Set endianness before we access any non-PCI registers. */=0A= #if BYTE_ORDER =3D=3D BIG_ENDIAN=0A= pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,=0A= BGE_BIGENDIAN_INIT, 4);=0A= #else=0A= pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,=0A= BGE_LITTLEENDIAN_INIT, 4);=0A= #endif=0A= =0A= /*=0A= * Check the 'ROM failed' bit on the RX CPU to see if=0A= * self-tests passed.=0A= */=0A= if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {=0A= printf("bge%d: RX CPU self-diagnostics failed!\n",=0A= sc->bge_unit);=0A= return(ENODEV);=0A= }=0A= =0A= /* Clear the MAC control register */=0A= CSR_WRITE_4(sc, BGE_MAC_MODE, 0);=0A= =0A= /*=0A= * Clear the MAC statistics block in the NIC's=0A= * internal memory.=0A= */=0A= for (i =3D BGE_STATS_BLOCK;=0A= i < BGE_STATS_BLOCK_END + 1; i +=3D sizeof(u_int32_t))=0A= BGE_MEMWIN_WRITE(sc, i, 0);=0A= =0A= for (i =3D BGE_STATUS_BLOCK;=0A= i < BGE_STATUS_BLOCK_END + 1; i +=3D sizeof(u_int32_t))=0A= BGE_MEMWIN_WRITE(sc, i, 0);=0A= =0A= /* Set up the PCI DMA control register. */=0A= if (sc->bge_pcie) {=0A= dma_rw_ctl =3D BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |=0A= (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |=0A= (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);=0A= } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &=0A= BGE_PCISTATE_PCI_BUSMODE) {=0A= /* Conventional PCI bus */=0A= dma_rw_ctl =3D BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |=0A= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |=0A= (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |=0A= (0x0F);=0A= } else {=0A= /* PCI-X bus */=0A= /*=0A= * The 5704 uses a different encoding of read/write=0A= * watermarks.=0A= */=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5704)=0A= dma_rw_ctl =3D BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |=0A= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |=0A= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);=0A= else=0A= dma_rw_ctl =3D BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |=0A= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |=0A= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |=0A= (0x0F);=0A= =0A= /*=0A= * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround=0A= * for hardware bugs.=0A= */=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5703 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5704) {=0A= u_int32_t tmp;=0A= =0A= tmp =3D CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;=0A= if (tmp =3D=3D 0x6 || tmp =3D=3D 0x7)=0A= dma_rw_ctl |=3D BGE_PCIDMARWCTL_ONEDMA_ATONCE;=0A= }=0A= }=0A= =0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5703 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5704 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5705 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5750)=0A= dma_rw_ctl &=3D ~BGE_PCIDMARWCTL_MINDMA;=0A= pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);=0A= =0A= /*=0A= * Set up general mode register.=0A= */=0A= CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|=0A= BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|=0A= BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|=0A= BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);=0A= =0A= /*=0A= * Disable memory write invalidate. Apparently it is not supported=0A= * properly by these devices.=0A= */=0A= PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);=0A= =0A= #ifdef __brokenalpha__=0A= /*=0A= * Must insure that we do not cross an 8K (bytes) boundary=0A= * for DMA reads. Our highest limit is 1K bytes. This is a=0A= * restriction on some ALPHA platforms with early revision=0A= * 21174 PCI chipsets, such as the AlphaPC 164lx=0A= */=0A= PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL,=0A= BGE_PCI_READ_BNDRY_1024BYTES, 4);=0A= #endif=0A= =0A= /* Set the timer prescaler (always 66Mhz) */=0A= CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);=0A= =0A= return(0);=0A= }=0A= =0A= static int=0A= bge_blockinit(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct bge_rcb *rcb;=0A= volatile struct bge_rcb *vrcb;=0A= int i;=0A= =0A= /*=0A= * Initialize the memory window pointer register so that=0A= * we can access the first 32K of internal NIC RAM. This will=0A= * allow us to set up the TX send ring RCBs and the RX return=0A= * ring RCBs, plus other things which live in NIC memory.=0A= */=0A= CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);=0A= =0A= /* Note: the BCM5704 has a smaller mbuf space than other chips. */=0A= =0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= /* Configure mbuf memory pool */=0A= if (sc->bge_extram) {=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,=0A= BGE_EXT_SSRAM);=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5704)=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);=0A= else=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);=0A= } else {=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,=0A= BGE_BUFFPOOL_1);=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5704)=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);=0A= else=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);=0A= }=0A= =0A= /* Configure DMA resource pool */=0A= CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,=0A= BGE_DMA_DESCRIPTORS);=0A= CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);=0A= }=0A= =0A= /* Configure mbuf pool watermarks */=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5705 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5750) {=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);=0A= } else {=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);=0A= }=0A= CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);=0A= =0A= /* Configure DMA resource watermarks */=0A= CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);=0A= CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);=0A= =0A= /* Enable buffer manager */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= CSR_WRITE_4(sc, BGE_BMAN_MODE,=0A= BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);=0A= =0A= /* Poll for buffer manager start indication */=0A= for (i =3D 0; i < BGE_TIMEOUT; i++) {=0A= if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)=0A= break;=0A= DELAY(10);=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: buffer manager failed to start\n",=0A= sc->bge_unit);=0A= return(ENXIO);=0A= }=0A= }=0A= =0A= /* Enable flow-through queues */=0A= CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);=0A= CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);=0A= =0A= /* Wait until queue initialization is complete */=0A= for (i =3D 0; i < BGE_TIMEOUT; i++) {=0A= if (CSR_READ_4(sc, BGE_FTQ_RESET) =3D=3D 0)=0A= break;=0A= DELAY(10);=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: flow-through queue init failed\n",=0A= sc->bge_unit);=0A= return(ENXIO);=0A= }=0A= =0A= /* Initialize the standard RX ring control block */=0A= rcb =3D &sc->bge_ldata.bge_info.bge_std_rx_rcb;=0A= rcb->bge_hostaddr.bge_addr_lo =3D=0A= BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);=0A= rcb->bge_hostaddr.bge_addr_hi =3D=0A= BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);=0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5705 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5750)=0A= rcb->bge_maxlen_flags =3D BGE_RCB_MAXLEN_FLAGS(512, 0);=0A= else=0A= rcb->bge_maxlen_flags =3D=0A= BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);=0A= if (sc->bge_extram)=0A= rcb->bge_nicaddr =3D BGE_EXT_STD_RX_RINGS;=0A= else=0A= rcb->bge_nicaddr =3D BGE_STD_RX_RINGS;=0A= CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, = rcb->bge_hostaddr.bge_addr_hi);=0A= CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, = rcb->bge_hostaddr.bge_addr_lo);=0A= =0A= CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, = rcb->bge_maxlen_flags);=0A= CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);=0A= =0A= /*=0A= * Initialize the jumbo RX ring control block=0A= * We set the 'ring disabled' bit in the flags=0A= * field until we're actually ready to start=0A= * using this ring (i.e. once we set the MTU=0A= * high enough to require it).=0A= */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= rcb =3D &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;=0A= =0A= rcb->bge_hostaddr.bge_addr_lo =3D=0A= BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);=0A= rcb->bge_hostaddr.bge_addr_hi =3D=0A= BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);=0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map,=0A= BUS_DMASYNC_PREREAD);=0A= rcb->bge_maxlen_flags =3D=0A= BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,=0A= BGE_RCB_FLAG_RING_DISABLED);=0A= if (sc->bge_extram)=0A= rcb->bge_nicaddr =3D BGE_EXT_JUMBO_RX_RINGS;=0A= else=0A= rcb->bge_nicaddr =3D BGE_JUMBO_RX_RINGS;=0A= CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,=0A= rcb->bge_hostaddr.bge_addr_hi);=0A= CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,=0A= rcb->bge_hostaddr.bge_addr_lo);=0A= =0A= CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,=0A= rcb->bge_maxlen_flags);=0A= CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);=0A= =0A= /* Set up dummy disabled mini ring RCB */=0A= rcb =3D &sc->bge_ldata.bge_info.bge_mini_rx_rcb;=0A= rcb->bge_maxlen_flags =3D=0A= BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);=0A= CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,=0A= rcb->bge_maxlen_flags);=0A= }=0A= =0A= /*=0A= * Set the BD ring replentish thresholds. The recommended=0A= * values are 1/8th the number of descriptors allocated to=0A= * each ring.=0A= */=0A= CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);=0A= CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, = BGE_JUMBO_RX_RING_CNT/8);=0A= =0A= /*=0A= * Disable all unused send rings by setting the 'ring disabled'=0A= * bit in the flags field of all the TX send ring control blocks.=0A= * These are located in NIC memory.=0A= */=0A= vrcb =3D (volatile struct bge_rcb *)(sc->bge_vhandle + = BGE_MEMWIN_START +=0A= BGE_SEND_RING_RCB);=0A= for (i =3D 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {=0A= vrcb->bge_maxlen_flags =3D=0A= BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);=0A= vrcb->bge_nicaddr =3D 0;=0A= vrcb++;=0A= }=0A= =0A= /* Configure TX RCB 0 (we use only the first ring) */=0A= vrcb =3D (volatile struct bge_rcb *)(sc->bge_vhandle + = BGE_MEMWIN_START +=0A= BGE_SEND_RING_RCB);=0A= vrcb->bge_hostaddr.bge_addr_lo =3D=0A= htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr));=0A= vrcb->bge_hostaddr.bge_addr_hi =3D=0A= htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr));=0A= vrcb->bge_nicaddr =3D BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= vrcb->bge_maxlen_flags =3D=0A= BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);=0A= =0A= /* Disable all unused RX return rings */=0A= vrcb =3D (volatile struct bge_rcb *)(sc->bge_vhandle + = BGE_MEMWIN_START +=0A= BGE_RX_RETURN_RING_RCB);=0A= for (i =3D 0; i < BGE_RX_RINGS_MAX; i++) {=0A= vrcb->bge_hostaddr.bge_addr_hi =3D 0;=0A= vrcb->bge_hostaddr.bge_addr_lo =3D 0;=0A= vrcb->bge_maxlen_flags =3D=0A= BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,=0A= BGE_RCB_FLAG_RING_DISABLED);=0A= vrcb->bge_nicaddr =3D 0;=0A= CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +=0A= (i * (sizeof(u_int64_t))), 0);=0A= vrcb++;=0A= }=0A= =0A= /* Initialize RX ring indexes */=0A= CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);=0A= CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);=0A= CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);=0A= =0A= /*=0A= * Set up RX return ring 0=0A= * Note that the NIC address for RX return rings is 0x00000000.=0A= * The return rings live entirely within the host, so the=0A= * nicaddr field in the RCB isn't used.=0A= */=0A= vrcb =3D (volatile struct bge_rcb *)(sc->bge_vhandle + = BGE_MEMWIN_START +=0A= BGE_RX_RETURN_RING_RCB);=0A= vrcb->bge_hostaddr.bge_addr_lo =3D=0A= BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr);=0A= vrcb->bge_hostaddr.bge_addr_hi =3D=0A= BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr);=0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,=0A= sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);=0A= vrcb->bge_nicaddr =3D 0x00000000;=0A= vrcb->bge_maxlen_flags =3D=0A= BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);=0A= =0A= /* Set random backoff seed for TX */=0A= CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,=0A= sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +=0A= sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +=0A= sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +=0A= BGE_TX_BACKOFF_SEED_MASK);=0A= =0A= /* Set inter-packet gap */=0A= CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);=0A= =0A= /*=0A= * Specify which ring to use for packets that don't match=0A= * any RX rules.=0A= */=0A= CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);=0A= =0A= /*=0A= * Configure number of RX lists. One interrupt distribution=0A= * list, sixteen active lists, one bad frames class.=0A= */=0A= CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);=0A= =0A= /* Inialize RX list placement stats mask. */=0A= CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);=0A= CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);=0A= =0A= /* Disable host coalescing until we get it set up */=0A= CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);=0A= =0A= /* Poll to make sure it's shut down. */=0A= for (i =3D 0; i < BGE_TIMEOUT; i++) {=0A= if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))=0A= break;=0A= DELAY(10);=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: host coalescing engine failed to idle\n",=0A= sc->bge_unit);=0A= return(ENXIO);=0A= }=0A= =0A= /* Set up host coalescing defaults */=0A= CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);=0A= CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);=0A= CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);=0A= CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);=0A= CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);=0A= }=0A= CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);=0A= CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);=0A= =0A= /* Set up address of statistics block */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,=0A= BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));=0A= CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,=0A= BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));=0A= CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);=0A= CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);=0A= CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);=0A= }=0A= =0A= /* Set up address of status block */=0A= CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,=0A= BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));=0A= CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,=0A= BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));=0A= bus_dmamap_sync(sc->bge_cdata.bge_status_tag,=0A= sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE);=0A= sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx =3D 0;=0A= sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx =3D 0;=0A= =0A= /* Turn on host coalescing state machine */=0A= CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);=0A= =0A= /* Turn on RX BD completion state machine and enable attentions */=0A= CSR_WRITE_4(sc, BGE_RBDC_MODE,=0A= BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);=0A= =0A= /* Turn on RX list placement state machine */=0A= CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);=0A= =0A= /* Turn on RX list selector state machine. */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);=0A= =0A= /* Turn on DMA, clear stats */=0A= CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|=0A= BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|=0A= BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|=0A= BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|=0A= (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));=0A= =0A= /* Set misc. local control, enable interrupts on attentions */=0A= CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);=0A= =0A= #ifdef notdef=0A= /* Assert GPIO pins for PHY reset */=0A= BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|=0A= BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);=0A= BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|=0A= BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);=0A= #endif=0A= =0A= /* Turn on DMA completion state machine */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);=0A= =0A= /* Turn on write DMA state machine */=0A= CSR_WRITE_4(sc, BGE_WDMA_MODE,=0A= BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);=0A= =0A= /* Turn on read DMA state machine */=0A= CSR_WRITE_4(sc, BGE_RDMA_MODE,=0A= BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);=0A= =0A= /* Turn on RX data completion state machine */=0A= CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);=0A= =0A= /* Turn on RX BD initiator state machine */=0A= CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);=0A= =0A= /* Turn on RX data and RX BD initiator state machine */=0A= CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);=0A= =0A= /* Turn on Mbuf cluster free state machine */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);=0A= =0A= /* Turn on send BD completion state machine */=0A= CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);=0A= =0A= /* Turn on send data completion state machine */=0A= CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);=0A= =0A= /* Turn on send data initiator state machine */=0A= CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);=0A= =0A= /* Turn on send BD initiator state machine */=0A= CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);=0A= =0A= /* Turn on send BD selector state machine */=0A= CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);=0A= =0A= CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);=0A= CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,=0A= BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);=0A= =0A= /* ack/clear link change events */=0A= CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|=0A= BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|=0A= BGE_MACSTAT_LINK_CHANGED);=0A= CSR_WRITE_4(sc, BGE_MI_STS, 0);=0A= =0A= /* Enable PHY auto polling (for MII/GMII only) */=0A= if (sc->bge_tbi) {=0A= CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);=0A= } else {=0A= BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5700)=0A= CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,=0A= BGE_EVTENB_MI_INTERRUPT);=0A= }=0A= =0A= /* Enable link state change attentions. */=0A= BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);=0A= =0A= return(0);=0A= }=0A= =0A= /*=0A= * Probe for a Broadcom chip. Check the PCI vendor and device IDs=0A= * against our list and return its name if we find a match. Note=0A= * that since the Broadcom controller contains VPD support, we=0A= * can get the device name string from the controller itself instead=0A= * of the compiled-in string. This is a little slow, but it = guarantees=0A= * we'll always announce the right product name.=0A= */=0A= static int=0A= bge_probe(dev)=0A= device_t dev;=0A= {=0A= struct bge_type *t;=0A= struct bge_softc *sc;=0A= char *descbuf;=0A= =0A= t =3D bge_devs;=0A= =0A= sc =3D device_get_softc(dev);=0A= bzero(sc, sizeof(struct bge_softc));=0A= sc->bge_unit =3D device_get_unit(dev);=0A= sc->bge_dev =3D dev;=0A= =0A= while(t->bge_name !=3D NULL) {=0A= if ((pci_get_vendor(dev) =3D=3D t->bge_vid) &&=0A= (pci_get_device(dev) =3D=3D t->bge_did)) {=0A= #ifdef notdef=0A= bge_vpd_read(sc);=0A= device_set_desc(dev, sc->bge_vpd_prodname);=0A= #endif=0A= descbuf =3D malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT);=0A= if (descbuf =3D=3D NULL)=0A= return(ENOMEM);=0A= snprintf(descbuf, BGE_DEVDESC_MAX,=0A= "%s, ASIC rev. %#04x", t->bge_name,=0A= pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);=0A= device_set_desc_copy(dev, descbuf);=0A= if (pci_get_subvendor(dev) =3D=3D DELL_VENDORID)=0A= sc->bge_no_3_led =3D 1;=0A= free(descbuf, M_TEMP);=0A= return(0);=0A= }=0A= t++;=0A= }=0A= =0A= return(ENXIO);=0A= }=0A= =0A= static void=0A= bge_dma_free(sc)=0A= struct bge_softc *sc;=0A= {=0A= int i;=0A= =0A= =0A= /* Destroy DMA maps for RX buffers */=0A= =0A= for (i =3D 0; i < BGE_STD_RX_RING_CNT; i++) {=0A= if (sc->bge_cdata.bge_rx_std_dmamap[i])=0A= bus_dmamap_destroy(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_rx_std_dmamap[i]);=0A= }=0A= =0A= /* Destroy DMA maps for jumbo RX buffers */=0A= =0A= for (i =3D 0; i < BGE_JUMBO_RX_RING_CNT; i++) {=0A= if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])=0A= bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,=0A= sc->bge_cdata.bge_rx_jumbo_dmamap[i]);=0A= }=0A= =0A= /* Destroy DMA maps for TX buffers */=0A= =0A= for (i =3D 0; i < BGE_TX_RING_CNT; i++) {=0A= if (sc->bge_cdata.bge_tx_dmamap[i])=0A= bus_dmamap_destroy(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_tx_dmamap[i]);=0A= }=0A= =0A= if (sc->bge_cdata.bge_mtag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_mtag);=0A= =0A= =0A= /* Destroy standard RX ring */=0A= =0A= if (sc->bge_ldata.bge_rx_std_ring)=0A= bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_ldata.bge_rx_std_ring,=0A= sc->bge_cdata.bge_rx_std_ring_map);=0A= =0A= if (sc->bge_cdata.bge_rx_std_ring_map) {=0A= bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_cdata.bge_rx_std_ring_map);=0A= bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_cdata.bge_rx_std_ring_map);=0A= }=0A= =0A= if (sc->bge_cdata.bge_rx_std_ring_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);=0A= =0A= /* Destroy jumbo RX ring */=0A= =0A= if (sc->bge_ldata.bge_rx_jumbo_ring)=0A= bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_ldata.bge_rx_jumbo_ring,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map);=0A= =0A= if (sc->bge_cdata.bge_rx_jumbo_ring_map) {=0A= bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map);=0A= bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map);=0A= }=0A= =0A= if (sc->bge_cdata.bge_rx_jumbo_ring_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);=0A= =0A= /* Destroy RX return ring */=0A= =0A= if (sc->bge_ldata.bge_rx_return_ring)=0A= bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,=0A= sc->bge_ldata.bge_rx_return_ring,=0A= sc->bge_cdata.bge_rx_return_ring_map);=0A= =0A= if (sc->bge_cdata.bge_rx_return_ring_map) {=0A= bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,=0A= sc->bge_cdata.bge_rx_return_ring_map);=0A= bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag,=0A= sc->bge_cdata.bge_rx_return_ring_map);=0A= }=0A= =0A= if (sc->bge_cdata.bge_rx_return_ring_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);=0A= =0A= /* Destroy TX ring */=0A= =0A= if (sc->bge_ldata.bge_tx_ring)=0A= bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,=0A= sc->bge_ldata.bge_tx_ring,=0A= sc->bge_cdata.bge_tx_ring_map);=0A= =0A= if (sc->bge_cdata.bge_tx_ring_map) {=0A= bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,=0A= sc->bge_cdata.bge_tx_ring_map);=0A= bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag,=0A= sc->bge_cdata.bge_tx_ring_map);=0A= }=0A= =0A= if (sc->bge_cdata.bge_tx_ring_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);=0A= =0A= /* Destroy status block */=0A= =0A= if (sc->bge_ldata.bge_status_block)=0A= bus_dmamem_free(sc->bge_cdata.bge_status_tag,=0A= sc->bge_ldata.bge_status_block,=0A= sc->bge_cdata.bge_status_map);=0A= =0A= if (sc->bge_cdata.bge_status_map) {=0A= bus_dmamap_unload(sc->bge_cdata.bge_status_tag,=0A= sc->bge_cdata.bge_status_map);=0A= bus_dmamap_destroy(sc->bge_cdata.bge_status_tag,=0A= sc->bge_cdata.bge_status_map);=0A= }=0A= =0A= if (sc->bge_cdata.bge_status_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);=0A= =0A= /* Destroy statistics block */=0A= =0A= if (sc->bge_ldata.bge_stats)=0A= bus_dmamem_free(sc->bge_cdata.bge_stats_tag,=0A= sc->bge_ldata.bge_stats,=0A= sc->bge_cdata.bge_stats_map);=0A= =0A= if (sc->bge_cdata.bge_stats_map) {=0A= bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,=0A= sc->bge_cdata.bge_stats_map);=0A= bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag,=0A= sc->bge_cdata.bge_stats_map);=0A= }=0A= =0A= if (sc->bge_cdata.bge_stats_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);=0A= =0A= /* Destroy the parent tag */=0A= =0A= if (sc->bge_cdata.bge_parent_tag)=0A= bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);=0A= =0A= return;=0A= }=0A= =0A= static int=0A= bge_dma_alloc(dev)=0A= device_t dev;=0A= {=0A= struct bge_softc *sc;=0A= int nseg, i, error;=0A= struct bge_dmamap_arg ctx;=0A= =0A= sc =3D device_get_softc(dev);=0A= =0A= /*=0A= * Allocate the parent bus DMA tag appropriate for PCI.=0A= */=0A= #define BGE_NSEG_NEW 32=0A= error =3D bus_dma_tag_create(NULL, /* parent */=0A= PAGE_SIZE, 0, /* alignment, boundary */=0A= BUS_SPACE_MAXADDR, /* lowaddr */=0A= BUS_SPACE_MAXADDR_32BIT,/* highaddr */=0A= NULL, NULL, /* filter, filterarg */=0A= MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */=0A= BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */=0A= 0, /* flags */=0A= NULL, NULL, /* lockfunc, lockarg */=0A= &sc->bge_cdata.bge_parent_tag);=0A= =0A= /*=0A= * Create tag for RX mbufs.=0A= */=0A= nseg =3D 32;=0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1,=0A= 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, NULL, = NULL,=0A= &sc->bge_cdata.bge_mtag);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Create DMA maps for RX buffers */=0A= =0A= for (i =3D 0; i < BGE_STD_RX_RING_CNT; i++) {=0A= error =3D bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,=0A= &sc->bge_cdata.bge_rx_std_dmamap[i]);=0A= if (error) {=0A= device_printf(dev, "can't create DMA map for RX\n");=0A= return(ENOMEM);=0A= }=0A= }=0A= =0A= /* Create DMA maps for TX buffers */=0A= =0A= for (i =3D 0; i < BGE_TX_RING_CNT; i++) {=0A= error =3D bus_dmamap_create(sc->bge_cdata.bge_mtag, 0,=0A= &sc->bge_cdata.bge_tx_dmamap[i]);=0A= if (error) {=0A= device_printf(dev, "can't create DMA map for RX\n");=0A= return(ENOMEM);=0A= }=0A= }=0A= =0A= /* Create tag for standard RX ring */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0,=0A= NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Allocate DMA'able memory for standard RX ring */=0A= =0A= error =3D bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag,=0A= (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT,=0A= &sc->bge_cdata.bge_rx_std_ring_map);=0A= if (error)=0A= return (ENOMEM);=0A= =0A= bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);=0A= =0A= /* Load the address of the standard RX ring */=0A= =0A= ctx.bge_maxsegs =3D 1;=0A= ctx.sc =3D sc;=0A= =0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_cdata.bge_rx_std_ring_map, = sc->bge_ldata.bge_rx_std_ring,=0A= BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= =0A= if (error)=0A= return (ENOMEM);=0A= =0A= sc->bge_ldata.bge_rx_std_ring_paddr =3D ctx.bge_busaddr;=0A= =0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= =0A= /*=0A= * Create tag for jumbo mbufs.=0A= * This is really a bit of a kludge. We allocate a special=0A= * jumbo buffer pool which (thanks to the way our DMA=0A= * memory allocation works) will consist of contiguous=0A= * pages. This means that even though a jumbo buffer might=0A= * be larger than a page size, we don't really need to=0A= * map it into more than one DMA segment. However, the=0A= * default mbuf tag will result in multi-segment mappings,=0A= * so we have to create a special jumbo mbuf tag that=0A= * lets us get away with mapping the jumbo buffers as=0A= * a single segment. I think eventually the driver should=0A= * be changed so that it uses ordinary mbufs and cluster=0A= * buffers, i.e. jumbo frames can span multiple DMA=0A= * descriptors. But that's a project for another day.=0A= */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL,=0A= &sc->bge_cdata.bge_mtag_jumbo);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Create tag for jumbo RX ring */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0,=0A= NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Allocate DMA'able memory for jumbo RX ring */=0A= =0A= error =3D bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT,=0A= &sc->bge_cdata.bge_rx_jumbo_ring_map);=0A= if (error)=0A= return (ENOMEM);=0A= =0A= bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring,=0A= BGE_JUMBO_RX_RING_SZ);=0A= =0A= /* Load the address of the jumbo RX ring */=0A= =0A= ctx.bge_maxsegs =3D 1;=0A= ctx.sc =3D sc;=0A= =0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map,=0A= sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ,=0A= bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= =0A= if (error)=0A= return (ENOMEM);=0A= =0A= sc->bge_ldata.bge_rx_jumbo_ring_paddr =3D ctx.bge_busaddr;=0A= =0A= /* Create DMA maps for jumbo RX buffers */=0A= =0A= for (i =3D 0; i < BGE_JUMBO_RX_RING_CNT; i++) {=0A= error =3D bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,=0A= 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);=0A= if (error) {=0A= device_printf(dev,=0A= "can't create DMA map for RX\n");=0A= return(ENOMEM);=0A= }=0A= }=0A= =0A= }=0A= =0A= /* Create tag for RX return ring */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0,=0A= NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Allocate DMA'able memory for RX return ring */=0A= =0A= error =3D bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag,=0A= (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT,=0A= &sc->bge_cdata.bge_rx_return_ring_map);=0A= if (error)=0A= return (ENOMEM);=0A= =0A= bzero((char *)sc->bge_ldata.bge_rx_return_ring,=0A= BGE_RX_RTN_RING_SZ(sc));=0A= =0A= /* Load the address of the RX return ring */=0A= =0A= ctx.bge_maxsegs =3D 1;=0A= ctx.sc =3D sc;=0A= =0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag,=0A= sc->bge_cdata.bge_rx_return_ring_map,=0A= sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc),=0A= bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= =0A= if (error)=0A= return (ENOMEM);=0A= =0A= sc->bge_ldata.bge_rx_return_ring_paddr =3D ctx.bge_busaddr;=0A= =0A= /* Create tag for TX ring */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL,=0A= &sc->bge_cdata.bge_tx_ring_tag);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Allocate DMA'able memory for TX ring */=0A= =0A= error =3D bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag,=0A= (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT,=0A= &sc->bge_cdata.bge_tx_ring_map);=0A= if (error)=0A= return (ENOMEM);=0A= =0A= bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);=0A= =0A= /* Load the address of the TX ring */=0A= =0A= ctx.bge_maxsegs =3D 1;=0A= ctx.sc =3D sc;=0A= =0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag,=0A= sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring,=0A= BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= =0A= if (error)=0A= return (ENOMEM);=0A= =0A= sc->bge_ldata.bge_tx_ring_paddr =3D ctx.bge_busaddr;=0A= =0A= /* Create tag for status block */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0,=0A= NULL, NULL, &sc->bge_cdata.bge_status_tag);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Allocate DMA'able memory for status block */=0A= =0A= error =3D bus_dmamem_alloc(sc->bge_cdata.bge_status_tag,=0A= (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT,=0A= &sc->bge_cdata.bge_status_map);=0A= if (error)=0A= return (ENOMEM);=0A= =0A= bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);=0A= =0A= /* Load the address of the status block */=0A= =0A= ctx.sc =3D sc;=0A= ctx.bge_maxsegs =3D 1;=0A= =0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_status_tag,=0A= sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block,=0A= BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= =0A= if (error)=0A= return (ENOMEM);=0A= =0A= sc->bge_ldata.bge_status_block_paddr =3D ctx.bge_busaddr;=0A= =0A= /* Create tag for statistics block */=0A= =0A= error =3D bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,=0A= PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,=0A= NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL,=0A= &sc->bge_cdata.bge_stats_tag);=0A= =0A= if (error) {=0A= device_printf(dev, "could not allocate dma tag\n");=0A= return (ENOMEM);=0A= }=0A= =0A= /* Allocate DMA'able memory for statistics block */=0A= =0A= error =3D bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag,=0A= (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT,=0A= &sc->bge_cdata.bge_stats_map);=0A= if (error)=0A= return (ENOMEM);=0A= =0A= bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ);=0A= =0A= /* Load the address of the statstics block */=0A= =0A= ctx.sc =3D sc;=0A= ctx.bge_maxsegs =3D 1;=0A= =0A= error =3D bus_dmamap_load(sc->bge_cdata.bge_stats_tag,=0A= sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats,=0A= BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);=0A= =0A= if (error)=0A= return (ENOMEM);=0A= =0A= sc->bge_ldata.bge_stats_paddr =3D ctx.bge_busaddr;=0A= =0A= return(0);=0A= }=0A= =0A= static int=0A= bge_attach(dev)=0A= device_t dev;=0A= {=0A= struct ifnet *ifp;=0A= struct bge_softc *sc;=0A= u_int32_t hwcfg =3D 0;=0A= u_int32_t mac_addr =3D 0;=0A= int unit, error =3D 0, rid;=0A= =0A= sc =3D device_get_softc(dev);=0A= unit =3D device_get_unit(dev);=0A= sc->bge_dev =3D dev;=0A= sc->bge_unit =3D unit;=0A= =0A= /*=0A= * Map control/status registers.=0A= */=0A= pci_enable_busmaster(dev);=0A= =0A= rid =3D BGE_PCI_BAR0;=0A= sc->bge_res =3D bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,=0A= RF_ACTIVE|PCI_RF_DENSE);=0A= =0A= if (sc->bge_res =3D=3D NULL) {=0A= printf ("bge%d: couldn't map memory\n", unit);=0A= error =3D ENXIO;=0A= goto fail;=0A= }=0A= =0A= sc->bge_btag =3D rman_get_bustag(sc->bge_res);=0A= sc->bge_bhandle =3D rman_get_bushandle(sc->bge_res);=0A= sc->bge_vhandle =3D (vm_offset_t)rman_get_virtual(sc->bge_res);=0A= =0A= /* Allocate interrupt */=0A= rid =3D 0;=0A= =0A= sc->bge_irq =3D bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,=0A= RF_SHAREABLE | RF_ACTIVE);=0A= =0A= if (sc->bge_irq =3D=3D NULL) {=0A= printf("bge%d: couldn't map interrupt\n", unit);=0A= error =3D ENXIO;=0A= goto fail;=0A= }=0A= =0A= sc->bge_unit =3D unit;=0A= =0A= BGE_LOCK_INIT(sc, device_get_nameunit(dev));=0A= =0A= /* Save ASIC rev. */=0A= =0A= sc->bge_chipid =3D=0A= pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &=0A= BGE_PCIMISCCTL_ASICREV;=0A= sc->bge_asicrev =3D BGE_ASICREV(sc->bge_chipid);=0A= sc->bge_chiprev =3D BGE_CHIPREV(sc->bge_chipid);=0A= =0A= /*=0A= * Treat the 5714 like the 5750 until we have more info=0A= * on this chip.=0A= */=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5714)=0A= sc->bge_asicrev =3D BGE_ASICREV_BCM5750;=0A= =0A= /*=0A= * XXX: Broadcom Linux driver. Not in specs or eratta.=0A= * PCI-Express?=0A= */=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5750) {=0A= u_int32_t v;=0A= =0A= v =3D pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);=0A= if (((v >> 8) & 0xff) =3D=3D BGE_PCIE_CAPID_REG) {=0A= v =3D pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);=0A= if ((v & 0xff) =3D=3D BGE_PCIE_CAPID)=0A= sc->bge_pcie =3D 1;=0A= }=0A= }=0A= =0A= /* Try to reset the chip. */=0A= bge_reset(sc);=0A= =0A= if (bge_chipinit(sc)) {=0A= printf("bge%d: chip initialization failed\n", sc->bge_unit);=0A= bge_release_resources(sc);=0A= error =3D ENXIO;=0A= goto fail;=0A= }=0A= =0A= /*=0A= * Get station address from the EEPROM.=0A= */=0A= mac_addr =3D bge_readmem_ind(sc, 0x0c14);=0A= if ((mac_addr >> 16) =3D=3D 0x484b) {=0A= sc->arpcom.ac_enaddr[0] =3D (u_char)(mac_addr >> 8);=0A= sc->arpcom.ac_enaddr[1] =3D (u_char)mac_addr;=0A= mac_addr =3D bge_readmem_ind(sc, 0x0c18);=0A= sc->arpcom.ac_enaddr[2] =3D (u_char)(mac_addr >> 24);=0A= sc->arpcom.ac_enaddr[3] =3D (u_char)(mac_addr >> 16);=0A= sc->arpcom.ac_enaddr[4] =3D (u_char)(mac_addr >> 8);=0A= sc->arpcom.ac_enaddr[5] =3D (u_char)mac_addr;=0A= } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr,=0A= BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {=0A= printf("bge%d: failed to read station address\n", unit);=0A= bge_release_resources(sc);=0A= error =3D ENXIO;=0A= goto fail;=0A= }=0A= =0A= /* 5705 limits RX return ring to 512 entries. */=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5705 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5750)=0A= sc->bge_return_ring_cnt =3D BGE_RETURN_RING_CNT_5705;=0A= else=0A= sc->bge_return_ring_cnt =3D BGE_RETURN_RING_CNT;=0A= =0A= if (bge_dma_alloc(dev)) {=0A= printf ("bge%d: failed to allocate DMA resources\n",=0A= sc->bge_unit);=0A= bge_release_resources(sc);=0A= error =3D ENXIO;=0A= goto fail;=0A= }=0A= =0A= /*=0A= * Try to allocate memory for jumbo buffers.=0A= * The 5705 does not appear to support jumbo frames.=0A= */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= if (bge_alloc_jumbo_mem(sc)) {=0A= printf("bge%d: jumbo buffer allocation "=0A= "failed\n", sc->bge_unit);=0A= bge_release_resources(sc);=0A= error =3D ENXIO;=0A= goto fail;=0A= }=0A= }=0A= =0A= /* Set default tuneable values. */=0A= sc->bge_stat_ticks =3D BGE_TICKS_PER_SEC;=0A= sc->bge_rx_coal_ticks =3D 150;=0A= sc->bge_tx_coal_ticks =3D 150;=0A= sc->bge_rx_max_coal_bds =3D 64;=0A= sc->bge_tx_max_coal_bds =3D 128;=0A= =0A= /* Set up ifnet structure */=0A= ifp =3D &sc->arpcom.ac_if;=0A= ifp->if_softc =3D sc;=0A= if_initname(ifp, device_get_name(dev), device_get_unit(dev));=0A= ifp->if_flags =3D IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;=0A= ifp->if_ioctl =3D bge_ioctl;=0A= ifp->if_start =3D bge_start;=0A= ifp->if_watchdog =3D bge_watchdog;=0A= ifp->if_init =3D bge_init;=0A= ifp->if_mtu =3D ETHERMTU;=0A= ifp->if_snd.ifq_maxlen =3D BGE_TX_RING_CNT - 1;=0A= ifp->if_hwassist =3D BGE_CSUM_FEATURES;=0A= /* NB: the code for RX csum offload is disabled for now */=0A= ifp->if_capabilities =3D IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING |=0A= IFCAP_VLAN_MTU;=0A= ifp->if_capenable =3D ifp->if_capabilities;=0A= =0A= /*=0A= * Figure out what sort of media we have by checking the=0A= * hardware config word in the first 32k of NIC internal memory,=0A= * or fall back to examining the EEPROM if necessary.=0A= * Note: on some BCM5700 cards, this value appears to be unset.=0A= * If that's the case, we have to rely on identifying the NIC=0A= * by its PCI subsystem ID, as we do below for the SysKonnect=0A= * SK-9D41.=0A= */=0A= if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) =3D=3D = BGE_MAGIC_NUMBER)=0A= hwcfg =3D bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);=0A= else {=0A= bge_read_eeprom(sc, (caddr_t)&hwcfg,=0A= BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));=0A= hwcfg =3D ntohl(hwcfg);=0A= }=0A= =0A= if ((hwcfg & BGE_HWCFG_MEDIA) =3D=3D BGE_MEDIA_FIBER)=0A= sc->bge_tbi =3D 1;=0A= =0A= /* The SysKonnect SK-9D41 is a 1000baseSX card. */=0A= if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) =3D=3D = SK_SUBSYSID_9D41)=0A= sc->bge_tbi =3D 1;=0A= =0A= if (sc->bge_tbi) {=0A= ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,=0A= bge_ifmedia_upd, bge_ifmedia_sts);=0A= ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);=0A= ifmedia_add(&sc->bge_ifmedia,=0A= IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);=0A= ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);=0A= ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);=0A= sc->bge_ifmedia.ifm_media =3D sc->bge_ifmedia.ifm_cur->ifm_media;=0A= } else {=0A= /*=0A= * Do transceiver setup.=0A= */=0A= if (mii_phy_probe(dev, &sc->bge_miibus,=0A= bge_ifmedia_upd, bge_ifmedia_sts)) {=0A= printf("bge%d: MII without any PHY!\n", sc->bge_unit);=0A= bge_release_resources(sc);=0A= bge_free_jumbo_mem(sc);=0A= error =3D ENXIO;=0A= goto fail;=0A= }=0A= }=0A= =0A= /*=0A= * When using the BCM5701 in PCI-X mode, data corruption has=0A= * been observed in the first few bytes of some received packets.=0A= * Aligning the packet buffer in memory eliminates the corruption.=0A= * Unfortunately, this misaligns the packet payloads. On platforms=0A= * which do not support unaligned accesses, we will realign the=0A= * payloads by copying the received packets.=0A= */=0A= switch (sc->bge_chipid) {=0A= case BGE_CHIPID_BCM5701_A0:=0A= case BGE_CHIPID_BCM5701_B0:=0A= case BGE_CHIPID_BCM5701_B2:=0A= case BGE_CHIPID_BCM5701_B5:=0A= /* If in PCI-X mode, work around the alignment bug. */=0A= if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &=0A= (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) =3D=3D=0A= BGE_PCISTATE_PCI_BUSSPEED)=0A= sc->bge_rx_alignment_bug =3D 1;=0A= break;=0A= }=0A= =0A= /*=0A= * Call MI attach routine.=0A= */=0A= ether_ifattach(ifp, sc->arpcom.ac_enaddr);=0A= callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE);=0A= =0A= /*=0A= * Hookup IRQ last.=0A= */=0A= error =3D bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | = INTR_MPSAFE,=0A= bge_intr, sc, &sc->bge_intrhand);=0A= =0A= if (error) {=0A= bge_release_resources(sc);=0A= printf("bge%d: couldn't set up irq\n", unit);=0A= }=0A= =0A= fail:=0A= return(error);=0A= }=0A= =0A= static int=0A= bge_detach(dev)=0A= device_t dev;=0A= {=0A= struct bge_softc *sc;=0A= struct ifnet *ifp;=0A= =0A= sc =3D device_get_softc(dev);=0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= BGE_LOCK(sc);=0A= bge_stop(sc);=0A= bge_reset(sc);=0A= BGE_UNLOCK(sc);=0A= =0A= ether_ifdetach(ifp);=0A= =0A= if (sc->bge_tbi) {=0A= ifmedia_removeall(&sc->bge_ifmedia);=0A= } else {=0A= bus_generic_detach(dev);=0A= device_delete_child(dev, sc->bge_miibus);=0A= }=0A= =0A= bge_release_resources(sc);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= bge_free_jumbo_mem(sc);=0A= =0A= return(0);=0A= }=0A= =0A= static void=0A= bge_release_resources(sc)=0A= struct bge_softc *sc;=0A= {=0A= device_t dev;=0A= =0A= dev =3D sc->bge_dev;=0A= =0A= if (sc->bge_vpd_prodname !=3D NULL)=0A= free(sc->bge_vpd_prodname, M_DEVBUF);=0A= =0A= if (sc->bge_vpd_readonly !=3D NULL)=0A= free(sc->bge_vpd_readonly, M_DEVBUF);=0A= =0A= if (sc->bge_intrhand !=3D NULL)=0A= bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);=0A= =0A= if (sc->bge_irq !=3D NULL)=0A= bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);=0A= =0A= if (sc->bge_res !=3D NULL)=0A= bus_release_resource(dev, SYS_RES_MEMORY,=0A= BGE_PCI_BAR0, sc->bge_res);=0A= =0A= bge_dma_free(sc);=0A= =0A= if (mtx_initialized(&sc->bge_mtx)) /* XXX */=0A= BGE_LOCK_DESTROY(sc);=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_reset(sc)=0A= struct bge_softc *sc;=0A= {=0A= device_t dev;=0A= u_int32_t cachesize, command, pcistate, reset;=0A= int i, val =3D 0;=0A= =0A= dev =3D sc->bge_dev;=0A= =0A= /* Save some important PCI state. */=0A= cachesize =3D pci_read_config(dev, BGE_PCI_CACHESZ, 4);=0A= command =3D pci_read_config(dev, BGE_PCI_CMD, 4);=0A= pcistate =3D pci_read_config(dev, BGE_PCI_PCISTATE, 4);=0A= =0A= pci_write_config(dev, BGE_PCI_MISC_CTL,=0A= BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|=0A= BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);=0A= =0A= reset =3D BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);=0A= =0A= /* XXX: Broadcom Linux driver. */=0A= if (sc->bge_pcie) {=0A= if (CSR_READ_4(sc, 0x7e2c) =3D=3D 0x60) /* PCIE 1.0 */=0A= CSR_WRITE_4(sc, 0x7e2c, 0x20);=0A= if (sc->bge_chipid !=3D BGE_CHIPID_BCM5750_A0) {=0A= /* Prevent PCIE link training during global reset */=0A= CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));=0A= reset |=3D (1<<29);=0A= }=0A= }=0A= =0A= /* Issue global reset */=0A= bge_writereg_ind(sc, BGE_MISC_CFG, reset);=0A= =0A= DELAY(1000);=0A= =0A= /* XXX: Broadcom Linux driver. */=0A= if (sc->bge_pcie) {=0A= if (sc->bge_chipid =3D=3D BGE_CHIPID_BCM5750_A0) {=0A= uint32_t v;=0A= =0A= DELAY(500000); /* wait for link training to complete */=0A= v =3D pci_read_config(dev, 0xc4, 4);=0A= pci_write_config(dev, 0xc4, v | (1<<15), 4);=0A= }=0A= /* Set PCIE max payload size and clear error status. */=0A= pci_write_config(dev, 0xd8, 0xf5000, 4);=0A= }=0A= =0A= /* Reset some of the PCI state that got zapped by reset */=0A= pci_write_config(dev, BGE_PCI_MISC_CTL,=0A= BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|=0A= BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);=0A= pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);=0A= pci_write_config(dev, BGE_PCI_CMD, command, 4);=0A= bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));=0A= =0A= /* Enable memory arbiter. */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);=0A= =0A= /*=0A= * Prevent PXE restart: write a magic number to the=0A= * general communications memory at 0xB50.=0A= */=0A= bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);=0A= /*=0A= * Poll the value location we just wrote until=0A= * we see the 1's complement of the magic number.=0A= * This indicates that the firmware initialization=0A= * is complete.=0A= */=0A= for (i =3D 0; i < BGE_TIMEOUT; i++) {=0A= val =3D bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);=0A= if (val =3D=3D ~BGE_MAGIC_NUMBER)=0A= break;=0A= DELAY(10);=0A= }=0A= =0A= if (i =3D=3D BGE_TIMEOUT) {=0A= printf("bge%d: firmware handshake timed out\n", sc->bge_unit);=0A= return;=0A= }=0A= =0A= /*=0A= * XXX Wait for the value of the PCISTATE register to=0A= * return to its original pre-reset state. This is a=0A= * fairly good indicator of reset completion. If we don't=0A= * wait for the reset to fully complete, trying to read=0A= * from the device's non-PCI registers may yield garbage=0A= * results.=0A= */=0A= for (i =3D 0; i < BGE_TIMEOUT; i++) {=0A= if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) =3D=3D pcistate)=0A= break;=0A= DELAY(10);=0A= }=0A= =0A= /* Fix up byte swapping */=0A= CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|=0A= BGE_MODECTL_BYTESWAP_DATA);=0A= =0A= CSR_WRITE_4(sc, BGE_MAC_MODE, 0);=0A= =0A= /*=0A= * The 5704 in TBI mode apparently needs some special=0A= * adjustment to insure the SERDES drive level is set=0A= * to 1.2V.=0A= */=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5704 && sc->bge_tbi) {=0A= uint32_t serdescfg;=0A= serdescfg =3D CSR_READ_4(sc, BGE_SERDES_CFG);=0A= serdescfg =3D (serdescfg & ~0xFFF) | 0x880;=0A= CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);=0A= }=0A= =0A= /* XXX: Broadcom Linux driver. */=0A= if (sc->bge_pcie && sc->bge_chipid !=3D BGE_CHIPID_BCM5750_A0) {=0A= uint32_t v;=0A= =0A= v =3D CSR_READ_4(sc, 0x7c00);=0A= CSR_WRITE_4(sc, 0x7c00, v | (1<<25));=0A= }=0A= DELAY(10000);=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Frame reception handling. This is called if there's a frame=0A= * on the receive return list.=0A= *=0A= * Note: we have to be able to handle two possibilities here:=0A= * 1) the frame is from the jumbo recieve ring=0A= * 2) the frame is from the standard receive ring=0A= */=0A= =0A= static void=0A= bge_rxeof(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct ifnet *ifp;=0A= int stdcnt =3D 0, jumbocnt =3D 0;=0A= =0A= BGE_LOCK_ASSERT(sc);=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,=0A= sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE);=0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map,=0A= BUS_DMASYNC_POSTREAD);=0A= }=0A= =0A= while(sc->bge_rx_saved_considx !=3D=0A= sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) {=0A= struct bge_rx_bd *cur_rx;=0A= u_int32_t rxidx;=0A= struct ether_header *eh;=0A= struct mbuf *m =3D NULL;=0A= u_int16_t vlan_tag =3D 0;=0A= int have_tag =3D 0;=0A= =0A= cur_rx =3D=0A= &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];=0A= =0A= rxidx =3D cur_rx->bge_idx;=0A= BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);=0A= =0A= if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {=0A= have_tag =3D 1;=0A= vlan_tag =3D cur_rx->bge_vlan_tag;=0A= }=0A= =0A= if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {=0A= BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);=0A= bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,=0A= sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx],=0A= BUS_DMASYNC_POSTREAD);=0A= bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,=0A= sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]);=0A= m =3D sc->bge_cdata.bge_rx_jumbo_chain[rxidx];=0A= sc->bge_cdata.bge_rx_jumbo_chain[rxidx] =3D NULL;=0A= jumbocnt++;=0A= if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {=0A= ifp->if_ierrors++;=0A= bge_newbuf_jumbo(sc, sc->bge_jumbo, m);=0A= continue;=0A= }=0A= if (bge_newbuf_jumbo(sc,=0A= sc->bge_jumbo, NULL) =3D=3D ENOBUFS) {=0A= ifp->if_ierrors++;=0A= bge_newbuf_jumbo(sc, sc->bge_jumbo, m);=0A= continue;=0A= }=0A= } else {=0A= BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);=0A= bus_dmamap_sync(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_rx_std_dmamap[rxidx],=0A= BUS_DMASYNC_POSTREAD);=0A= bus_dmamap_unload(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_rx_std_dmamap[rxidx]);=0A= m =3D sc->bge_cdata.bge_rx_std_chain[rxidx];=0A= sc->bge_cdata.bge_rx_std_chain[rxidx] =3D NULL;=0A= stdcnt++;=0A= if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {=0A= ifp->if_ierrors++;=0A= bge_newbuf_std(sc, sc->bge_std, m);=0A= continue;=0A= }=0A= if (bge_newbuf_std(sc, sc->bge_std,=0A= NULL) =3D=3D ENOBUFS) {=0A= ifp->if_ierrors++;=0A= bge_newbuf_std(sc, sc->bge_std, m);=0A= continue;=0A= }=0A= }=0A= =0A= ifp->if_ipackets++;=0A= #ifndef __i386__=0A= /*=0A= * The i386 allows unaligned accesses, but for other=0A= * platforms we must make sure the payload is aligned.=0A= */=0A= if (sc->bge_rx_alignment_bug) {=0A= bcopy(m->m_data, m->m_data + ETHER_ALIGN,=0A= cur_rx->bge_len);=0A= m->m_data +=3D ETHER_ALIGN;=0A= }=0A= #endif=0A= eh =3D mtod(m, struct ether_header *);=0A= m->m_pkthdr.len =3D m->m_len =3D cur_rx->bge_len - ETHER_CRC_LEN;=0A= m->m_pkthdr.rcvif =3D ifp;=0A= =0A= #if 0 /* currently broken for some packets, possibly related to TCP = options */=0A= if (ifp->if_capenable & IFCAP_RXCSUM) {=0A= m->m_pkthdr.csum_flags |=3D CSUM_IP_CHECKED;=0A= if ((cur_rx->bge_ip_csum ^ 0xffff) =3D=3D 0)=0A= m->m_pkthdr.csum_flags |=3D CSUM_IP_VALID;=0A= if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {=0A= m->m_pkthdr.csum_data =3D=0A= cur_rx->bge_tcp_udp_csum;=0A= m->m_pkthdr.csum_flags |=3D CSUM_DATA_VALID;=0A= }=0A= }=0A= #endif=0A= =0A= /*=0A= * If we received a packet with a vlan tag,=0A= * attach that information to the packet.=0A= */=0A= if (have_tag)=0A= VLAN_INPUT_TAG(ifp, m, vlan_tag, continue);=0A= =0A= BGE_UNLOCK(sc);=0A= (*ifp->if_input)(ifp, m);=0A= BGE_LOCK(sc);=0A= }=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,=0A= sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);=0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,=0A= sc->bge_cdata.bge_rx_std_ring_map,=0A= BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,=0A= sc->bge_cdata.bge_rx_jumbo_ring_map,=0A= BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);=0A= }=0A= =0A= CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);=0A= if (stdcnt)=0A= CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);=0A= if (jumbocnt)=0A= CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_txeof(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct bge_tx_bd *cur_tx =3D NULL;=0A= struct ifnet *ifp;=0A= =0A= BGE_LOCK_ASSERT(sc);=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= /*=0A= * Go through our tx ring and free mbufs for those=0A= * frames that have been sent.=0A= */=0A= while (sc->bge_tx_saved_considx !=3D=0A= sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) {=0A= u_int32_t idx =3D 0;=0A= =0A= idx =3D sc->bge_tx_saved_considx;=0A= cur_tx =3D &sc->bge_ldata.bge_tx_ring[idx];=0A= if (cur_tx->bge_flags & BGE_TXBDFLAG_END)=0A= ifp->if_opackets++;=0A= if (sc->bge_cdata.bge_tx_chain[idx] !=3D NULL) {=0A= m_freem(sc->bge_cdata.bge_tx_chain[idx]);=0A= sc->bge_cdata.bge_tx_chain[idx] =3D NULL;=0A= bus_dmamap_unload(sc->bge_cdata.bge_mtag,=0A= sc->bge_cdata.bge_tx_dmamap[idx]);=0A= }=0A= sc->bge_txcnt--;=0A= BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);=0A= ifp->if_timer =3D 0;=0A= }=0A= =0A= if (cur_tx !=3D NULL)=0A= ifp->if_flags &=3D ~IFF_OACTIVE;=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_intr(xsc)=0A= void *xsc;=0A= {=0A= struct bge_softc *sc;=0A= struct ifnet *ifp;=0A= u_int32_t statusword;=0A= u_int32_t status, mimode;=0A= =0A= sc =3D xsc;=0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= BGE_LOCK(sc);=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_status_tag,=0A= sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE);=0A= =0A= statusword =3D=0A= = atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status);=0A= =0A= #ifdef notdef=0A= /* Avoid this for now -- checking this register is expensive. */=0A= /* Make sure this is really our interrupt. */=0A= if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))=0A= return;=0A= #endif=0A= /* Ack interrupt and stop others from occuring. */=0A= CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);=0A= =0A= /*=0A= * Process link state changes.=0A= * Grrr. The link status word in the status block does=0A= * not work correctly on the BCM5700 rev AX and BX chips,=0A= * according to all available information. Hence, we have=0A= * to enable MII interrupts in order to properly obtain=0A= * async link changes. Unfortunately, this also means that=0A= * we have to read the MAC status register to detect link=0A= * changes, thereby adding an additional register access to=0A= * the interrupt handler.=0A= */=0A= =0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5700) {=0A= =0A= status =3D CSR_READ_4(sc, BGE_MAC_STS);=0A= if (status & BGE_MACSTAT_MI_INTERRUPT) {=0A= sc->bge_link =3D 0;=0A= callout_stop(&sc->bge_stat_ch);=0A= bge_tick_locked(sc);=0A= /* Clear the interrupt */=0A= CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,=0A= BGE_EVTENB_MI_INTERRUPT);=0A= bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);=0A= bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,=0A= BRGPHY_INTRS);=0A= }=0A= } else {=0A= if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {=0A= /*=0A= * Sometimes PCS encoding errors are detected in=0A= * TBI mode (on fiber NICs), and for some reason=0A= * the chip will signal them as link changes.=0A= * If we get a link change event, but the 'PCS=0A= * encoding error' bit in the MAC status register=0A= * is set, don't bother doing a link check.=0A= * This avoids spurious "gigabit link up" messages=0A= * that sometimes appear on fiber NICs during=0A= * periods of heavy traffic. (There should be no=0A= * effect on copper NICs.)=0A= *=0A= * If we do have a copper NIC (bge_tbi =3D=3D 0) then=0A= * check that the AUTOPOLL bit is set before=0A= * processing the event as a real link change.=0A= * Turning AUTOPOLL on and off in the MII read/write=0A= * functions will often trigger a link status=0A= * interrupt for no reason.=0A= */=0A= status =3D CSR_READ_4(sc, BGE_MAC_STS);=0A= mimode =3D CSR_READ_4(sc, BGE_MI_MODE);=0A= if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR|=0A= BGE_MACSTAT_MI_COMPLETE)) && (!sc->bge_tbi &&=0A= (mimode & BGE_MIMODE_AUTOPOLL))) {=0A= sc->bge_link =3D 0;=0A= callout_stop(&sc->bge_stat_ch);=0A= bge_tick_locked(sc);=0A= }=0A= /* Clear the interrupt */=0A= CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|=0A= BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|=0A= BGE_MACSTAT_LINK_CHANGED);=0A= =0A= /* Force flush the status block cached by PCI bridge */=0A= CSR_READ_4(sc, BGE_MBX_IRQ0_LO);=0A= }=0A= }=0A= =0A= if (ifp->if_flags & IFF_RUNNING) {=0A= /* Check RX return ring producer/consumer */=0A= bge_rxeof(sc);=0A= =0A= /* Check TX ring producer/consumer */=0A= bge_txeof(sc);=0A= }=0A= =0A= bus_dmamap_sync(sc->bge_cdata.bge_status_tag,=0A= sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE);=0A= =0A= bge_handle_events(sc);=0A= =0A= /* Re-enable interrupts. */=0A= CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);=0A= =0A= if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head !=3D NULL)=0A= bge_start_locked(ifp);=0A= =0A= BGE_UNLOCK(sc);=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_tick_locked(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct mii_data *mii =3D NULL;=0A= struct ifmedia *ifm =3D NULL;=0A= struct ifnet *ifp;=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= BGE_LOCK_ASSERT(sc);=0A= =0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5705 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5750)=0A= bge_stats_update_regs(sc);=0A= else=0A= bge_stats_update(sc);=0A= callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);=0A= if (sc->bge_link)=0A= return;=0A= =0A= if (sc->bge_tbi) {=0A= ifm =3D &sc->bge_ifmedia;=0A= if (CSR_READ_4(sc, BGE_MAC_STS) &=0A= BGE_MACSTAT_TBI_PCS_SYNCHED) {=0A= sc->bge_link++;=0A= if (sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5704)=0A= BGE_CLRBIT(sc, BGE_MAC_MODE,=0A= BGE_MACMODE_TBI_SEND_CFGS);=0A= CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);=0A= if (bootverbose)=0A= printf("bge%d: gigabit link up\n",=0A= sc->bge_unit);=0A= if (ifp->if_snd.ifq_head !=3D NULL)=0A= bge_start_locked(ifp);=0A= }=0A= return;=0A= }=0A= =0A= mii =3D device_get_softc(sc->bge_miibus);=0A= mii_tick(mii);=0A= =0A= if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE &&=0A= IFM_SUBTYPE(mii->mii_media_active) !=3D IFM_NONE) {=0A= sc->bge_link++;=0A= if ((IFM_SUBTYPE(mii->mii_media_active) =3D=3D IFM_1000_T ||=0A= IFM_SUBTYPE(mii->mii_media_active) =3D=3D IFM_1000_SX) &&=0A= bootverbose)=0A= printf("bge%d: gigabit link up\n", sc->bge_unit);=0A= if (ifp->if_snd.ifq_head !=3D NULL)=0A= bge_start_locked(ifp);=0A= }=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_tick(xsc)=0A= void *xsc;=0A= {=0A= struct bge_softc *sc;=0A= =0A= sc =3D xsc;=0A= =0A= BGE_LOCK(sc);=0A= bge_tick_locked(sc);=0A= BGE_UNLOCK(sc);=0A= }=0A= =0A= static void=0A= bge_stats_update_regs(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct ifnet *ifp;=0A= struct bge_mac_stats_regs stats;=0A= u_int32_t *s;=0A= int i;=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= s =3D (u_int32_t *)&stats;=0A= for (i =3D 0; i < sizeof(struct bge_mac_stats_regs); i +=3D 4) {=0A= *s =3D CSR_READ_4(sc, BGE_RX_STATS + i);=0A= s++;=0A= }=0A= =0A= ifp->if_collisions +=3D=0A= (stats.dot3StatsSingleCollisionFrames +=0A= stats.dot3StatsMultipleCollisionFrames +=0A= stats.dot3StatsExcessiveCollisions +=0A= stats.dot3StatsLateCollisions) -=0A= ifp->if_collisions;=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_stats_update(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct ifnet *ifp;=0A= struct bge_stats *stats;=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= stats =3D (struct bge_stats *)(sc->bge_vhandle +=0A= BGE_MEMWIN_START + BGE_STATS_BLOCK);=0A= =0A= ifp->if_collisions +=3D=0A= (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +=0A= stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +=0A= stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +=0A= stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -=0A= ifp->if_collisions;=0A= =0A= #ifdef notdef=0A= ifp->if_collisions +=3D=0A= (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames = +=0A= sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames = +=0A= sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +=0A= sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -=0A= ifp->if_collisions;=0A= #endif=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Encapsulate an mbuf chain in the tx ring by coupling the mbuf = data=0A= * pointers to descriptors.=0A= */=0A= static int=0A= bge_encap(sc, m_head, txidx)=0A= struct bge_softc *sc;=0A= struct mbuf *m_head;=0A= u_int32_t *txidx;=0A= {=0A= struct bge_tx_bd *f =3D NULL;=0A= u_int16_t csum_flags =3D 0;=0A= struct m_tag *mtag;=0A= struct bge_dmamap_arg ctx;=0A= bus_dmamap_t map;=0A= int error;=0A= =0A= =0A= if (m_head->m_pkthdr.csum_flags) {=0A= if (m_head->m_pkthdr.csum_flags & CSUM_IP)=0A= csum_flags |=3D BGE_TXBDFLAG_IP_CSUM;=0A= if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))=0A= csum_flags |=3D BGE_TXBDFLAG_TCP_UDP_CSUM;=0A= if (m_head->m_flags & M_LASTFRAG)=0A= csum_flags |=3D BGE_TXBDFLAG_IP_FRAG_END;=0A= else if (m_head->m_flags & M_FRAG)=0A= csum_flags |=3D BGE_TXBDFLAG_IP_FRAG;=0A= }=0A= =0A= mtag =3D VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head);=0A= =0A= ctx.sc =3D sc;=0A= ctx.bge_idx =3D *txidx;=0A= ctx.bge_ring =3D sc->bge_ldata.bge_tx_ring;=0A= ctx.bge_flags =3D csum_flags;=0A= /*=0A= * Sanity check: avoid coming within 16 descriptors=0A= * of the end of the ring.=0A= */=0A= ctx.bge_maxsegs =3D (BGE_TX_RING_CNT - sc->bge_txcnt) - 16;=0A= =0A= map =3D sc->bge_cdata.bge_tx_dmamap[*txidx];=0A= error =3D bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map,=0A= m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT);=0A= =0A= if (error || ctx.bge_maxsegs =3D=3D 0 /*||=0A= ctx.bge_idx =3D=3D sc->bge_tx_saved_considx*/)=0A= return (ENOBUFS);=0A= =0A= /*=0A= * Insure that the map for this transmission=0A= * is placed at the array index of the last descriptor=0A= * in this chain.=0A= */=0A= sc->bge_cdata.bge_tx_dmamap[*txidx] =3D=0A= sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx];=0A= sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] =3D map;=0A= sc->bge_cdata.bge_tx_chain[ctx.bge_idx] =3D m_head;=0A= sc->bge_txcnt +=3D ctx.bge_maxsegs;=0A= f =3D &sc->bge_ldata.bge_tx_ring[*txidx];=0A= if (mtag !=3D NULL) {=0A= f->bge_flags |=3D htole16(BGE_TXBDFLAG_VLAN_TAG);=0A= f->bge_vlan_tag =3D htole16(VLAN_TAG_VALUE(mtag));=0A= } else {=0A= f->bge_vlan_tag =3D 0;=0A= }=0A= =0A= BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT);=0A= *txidx =3D ctx.bge_idx;=0A= =0A= return(0);=0A= }=0A= =0A= /*=0A= * Main transmit routine. To avoid having to do mbuf copies, we put = pointers=0A= * to the mbuf data regions directly in the transmit descriptors.=0A= */=0A= static void=0A= bge_start_locked(ifp)=0A= struct ifnet *ifp;=0A= {=0A= struct bge_softc *sc;=0A= struct mbuf *m_head =3D NULL;=0A= u_int32_t prodidx =3D 0;=0A= int count =3D 0;=0A= =0A= sc =3D ifp->if_softc;=0A= =0A= if (!sc->bge_link && ifp->if_snd.ifq_len < 10)=0A= return;=0A= =0A= prodidx =3D CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);=0A= =0A= while(sc->bge_cdata.bge_tx_chain[prodidx] =3D=3D NULL) {=0A= IF_DEQUEUE(&ifp->if_snd, m_head);=0A= if (m_head =3D=3D NULL)=0A= break;=0A= =0A= /*=0A= * XXX=0A= * The code inside the if() block is never reached since we=0A= * must mark CSUM_IP_FRAGS in our if_hwassist to start getting=0A= * requests to checksum TCP/UDP in a fragmented packet.=0A= *=0A= * XXX=0A= * safety overkill. If this is a fragmented packet chain=0A= * with delayed TCP/UDP checksums, then only encapsulate=0A= * it if we have enough descriptors to handle the entire=0A= * chain at once.=0A= * (paranoia -- may not actually be needed)=0A= */=0A= if (m_head->m_flags & M_FIRSTFRAG &&=0A= m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {=0A= if ((BGE_TX_RING_CNT - sc->bge_txcnt) <=0A= m_head->m_pkthdr.csum_data + 16) {=0A= IF_PREPEND(&ifp->if_snd, m_head);=0A= ifp->if_flags |=3D IFF_OACTIVE;=0A= break;=0A= }=0A= }=0A= =0A= /*=0A= * Pack the data into the transmit ring. If we=0A= * don't have room, set the OACTIVE flag and wait=0A= * for the NIC to drain the ring.=0A= */=0A= if (bge_encap(sc, m_head, &prodidx)) {=0A= IF_PREPEND(&ifp->if_snd, m_head);=0A= ifp->if_flags |=3D IFF_OACTIVE;=0A= break;=0A= }=0A= ++count;=0A= =0A= /*=0A= * If there's a BPF listener, bounce a copy of this frame=0A= * to him.=0A= */=0A= BPF_MTAP(ifp, m_head);=0A= }=0A= =0A= if (count =3D=3D 0) {=0A= /* no packets were dequeued */=0A= return;=0A= }=0A= =0A= /* Transmit */=0A= CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);=0A= /* 5700 b2 errata */=0A= if (sc->bge_chiprev =3D=3D BGE_CHIPREV_5700_BX)=0A= CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);=0A= =0A= /*=0A= * Set a timeout in case the chip goes out to lunch.=0A= */=0A= ifp->if_timer =3D 5;=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Main transmit routine. To avoid having to do mbuf copies, we put = pointers=0A= * to the mbuf data regions directly in the transmit descriptors.=0A= */=0A= static void=0A= bge_start(ifp)=0A= struct ifnet *ifp;=0A= {=0A= struct bge_softc *sc;=0A= =0A= sc =3D ifp->if_softc;=0A= BGE_LOCK(sc);=0A= bge_start_locked(ifp);=0A= BGE_UNLOCK(sc);=0A= }=0A= =0A= static void=0A= bge_init_locked(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct ifnet *ifp;=0A= u_int16_t *m;=0A= =0A= BGE_LOCK_ASSERT(sc);=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= if (ifp->if_flags & IFF_RUNNING)=0A= return;=0A= =0A= /* Cancel pending I/O and flush buffers. */=0A= bge_stop(sc);=0A= bge_reset(sc);=0A= bge_chipinit(sc);=0A= =0A= /*=0A= * Init the various state machines, ring=0A= * control blocks and firmware.=0A= */=0A= if (bge_blockinit(sc)) {=0A= printf("bge%d: initialization failure\n", sc->bge_unit);=0A= return;=0A= }=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= /* Specify MTU. */=0A= CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +=0A= ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN);=0A= =0A= /* Load our MAC address. */=0A= m =3D (u_int16_t *)&sc->arpcom.ac_enaddr[0];=0A= CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));=0A= CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | = htons(m[2]));=0A= =0A= /* Enable or disable promiscuous mode as needed. */=0A= if (ifp->if_flags & IFF_PROMISC) {=0A= BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);=0A= } else {=0A= BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);=0A= }=0A= =0A= /* Program multicast filter. */=0A= bge_setmulti(sc);=0A= =0A= /* Init RX ring. */=0A= bge_init_rx_ring_std(sc);=0A= =0A= /*=0A= * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's=0A= * memory to insure that the chip has in fact read the first=0A= * entry of the ring.=0A= */=0A= if (sc->bge_chipid =3D=3D BGE_CHIPID_BCM5705_A0) {=0A= u_int32_t v, i;=0A= for (i =3D 0; i < 10; i++) {=0A= DELAY(20);=0A= v =3D bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);=0A= if (v =3D=3D (MCLBYTES - ETHER_ALIGN))=0A= break;=0A= }=0A= if (i =3D=3D 10)=0A= printf ("bge%d: 5705 A0 chip failed to load RX ring\n",=0A= sc->bge_unit);=0A= }=0A= =0A= /* Init jumbo RX ring. */=0A= if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))=0A= bge_init_rx_ring_jumbo(sc);=0A= =0A= /* Init our RX return ring index */=0A= sc->bge_rx_saved_considx =3D 0;=0A= =0A= /* Init TX ring. */=0A= bge_init_tx_ring(sc);=0A= =0A= /* Turn on transmitter */=0A= BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);=0A= =0A= /* Turn on receiver */=0A= BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);=0A= =0A= /* Tell firmware we're alive. */=0A= BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);=0A= =0A= /* Enable host interrupts. */=0A= BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);=0A= BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);=0A= CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);=0A= =0A= bge_ifmedia_upd(ifp);=0A= =0A= ifp->if_flags |=3D IFF_RUNNING;=0A= ifp->if_flags &=3D ~IFF_OACTIVE;=0A= =0A= callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);=0A= =0A= return;=0A= }=0A= =0A= static void=0A= bge_init(xsc)=0A= void *xsc;=0A= {=0A= struct bge_softc *sc =3D xsc;=0A= =0A= BGE_LOCK(sc);=0A= bge_init_locked(sc);=0A= BGE_UNLOCK(sc);=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Set media options.=0A= */=0A= static int=0A= bge_ifmedia_upd(ifp)=0A= struct ifnet *ifp;=0A= {=0A= struct bge_softc *sc;=0A= struct mii_data *mii;=0A= struct ifmedia *ifm;=0A= =0A= sc =3D ifp->if_softc;=0A= ifm =3D &sc->bge_ifmedia;=0A= =0A= /* If this is a 1000baseX NIC, enable the TBI port. */=0A= if (sc->bge_tbi) {=0A= if (IFM_TYPE(ifm->ifm_media) !=3D IFM_ETHER)=0A= return(EINVAL);=0A= switch(IFM_SUBTYPE(ifm->ifm_media)) {=0A= case IFM_AUTO:=0A= break;=0A= case IFM_1000_SX:=0A= if ((ifm->ifm_media & IFM_GMASK) =3D=3D IFM_FDX) {=0A= BGE_CLRBIT(sc, BGE_MAC_MODE,=0A= BGE_MACMODE_HALF_DUPLEX);=0A= } else {=0A= BGE_SETBIT(sc, BGE_MAC_MODE,=0A= BGE_MACMODE_HALF_DUPLEX);=0A= }=0A= break;=0A= default:=0A= return(EINVAL);=0A= }=0A= return(0);=0A= }=0A= =0A= mii =3D device_get_softc(sc->bge_miibus);=0A= sc->bge_link =3D 0;=0A= if (mii->mii_instance) {=0A= struct mii_softc *miisc;=0A= for (miisc =3D LIST_FIRST(&mii->mii_phys); miisc !=3D NULL;=0A= miisc =3D LIST_NEXT(miisc, mii_list))=0A= mii_phy_reset(miisc);=0A= }=0A= mii_mediachg(mii);=0A= =0A= return(0);=0A= }=0A= =0A= /*=0A= * Report current media status.=0A= */=0A= static void=0A= bge_ifmedia_sts(ifp, ifmr)=0A= struct ifnet *ifp;=0A= struct ifmediareq *ifmr;=0A= {=0A= struct bge_softc *sc;=0A= struct mii_data *mii;=0A= =0A= sc =3D ifp->if_softc;=0A= =0A= if (sc->bge_tbi) {=0A= ifmr->ifm_status =3D IFM_AVALID;=0A= ifmr->ifm_active =3D IFM_ETHER;=0A= if (CSR_READ_4(sc, BGE_MAC_STS) &=0A= BGE_MACSTAT_TBI_PCS_SYNCHED)=0A= ifmr->ifm_status |=3D IFM_ACTIVE;=0A= ifmr->ifm_active |=3D IFM_1000_SX;=0A= if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)=0A= ifmr->ifm_active |=3D IFM_HDX;=0A= else=0A= ifmr->ifm_active |=3D IFM_FDX;=0A= return;=0A= }=0A= =0A= mii =3D device_get_softc(sc->bge_miibus);=0A= mii_pollstat(mii);=0A= ifmr->ifm_active =3D mii->mii_media_active;=0A= ifmr->ifm_status =3D mii->mii_media_status;=0A= =0A= return;=0A= }=0A= =0A= static int=0A= bge_ioctl(ifp, command, data)=0A= struct ifnet *ifp;=0A= u_long command;=0A= caddr_t data;=0A= {=0A= struct bge_softc *sc =3D ifp->if_softc;=0A= struct ifreq *ifr =3D (struct ifreq *) data;=0A= int mask, error =3D 0;=0A= struct mii_data *mii;=0A= =0A= switch(command) {=0A= case SIOCSIFMTU:=0A= /* Disallow jumbo frames on 5705. */=0A= if (((sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5705 ||=0A= sc->bge_asicrev =3D=3D BGE_ASICREV_BCM5750) &&=0A= ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)=0A= error =3D EINVAL;=0A= else {=0A= ifp->if_mtu =3D ifr->ifr_mtu;=0A= ifp->if_flags &=3D ~IFF_RUNNING;=0A= bge_init(sc);=0A= }=0A= break;=0A= case SIOCSIFFLAGS:=0A= BGE_LOCK(sc);=0A= if (ifp->if_flags & IFF_UP) {=0A= /*=0A= * If only the state of the PROMISC flag changed,=0A= * then just use the 'set promisc mode' command=0A= * instead of reinitializing the entire NIC. Doing=0A= * a full re-init means reloading the firmware and=0A= * waiting for it to start up, which may take a=0A= * second or two.=0A= */=0A= if (ifp->if_flags & IFF_RUNNING &&=0A= ifp->if_flags & IFF_PROMISC &&=0A= !(sc->bge_if_flags & IFF_PROMISC)) {=0A= BGE_SETBIT(sc, BGE_RX_MODE,=0A= BGE_RXMODE_RX_PROMISC);=0A= } else if (ifp->if_flags & IFF_RUNNING &&=0A= !(ifp->if_flags & IFF_PROMISC) &&=0A= sc->bge_if_flags & IFF_PROMISC) {=0A= BGE_CLRBIT(sc, BGE_RX_MODE,=0A= BGE_RXMODE_RX_PROMISC);=0A= } else=0A= bge_init_locked(sc);=0A= } else {=0A= if (ifp->if_flags & IFF_RUNNING) {=0A= bge_stop(sc);=0A= }=0A= }=0A= sc->bge_if_flags =3D ifp->if_flags;=0A= BGE_UNLOCK(sc);=0A= error =3D 0;=0A= break;=0A= case SIOCADDMULTI:=0A= case SIOCDELMULTI:=0A= if (ifp->if_flags & IFF_RUNNING) {=0A= BGE_LOCK(sc);=0A= bge_setmulti(sc);=0A= BGE_UNLOCK(sc);=0A= error =3D 0;=0A= }=0A= break;=0A= case SIOCSIFMEDIA:=0A= case SIOCGIFMEDIA:=0A= if (sc->bge_tbi) {=0A= error =3D ifmedia_ioctl(ifp, ifr,=0A= &sc->bge_ifmedia, command);=0A= } else {=0A= mii =3D device_get_softc(sc->bge_miibus);=0A= error =3D ifmedia_ioctl(ifp, ifr,=0A= &mii->mii_media, command);=0A= }=0A= break;=0A= case SIOCSIFCAP:=0A= mask =3D ifr->ifr_reqcap ^ ifp->if_capenable;=0A= /* NB: the code for RX csum offload is disabled for now */=0A= if (mask & IFCAP_TXCSUM) {=0A= ifp->if_capenable ^=3D IFCAP_TXCSUM;=0A= if (IFCAP_TXCSUM & ifp->if_capenable)=0A= ifp->if_hwassist =3D BGE_CSUM_FEATURES;=0A= else=0A= ifp->if_hwassist =3D 0;=0A= }=0A= error =3D 0;=0A= break;=0A= default:=0A= error =3D ether_ioctl(ifp, command, data);=0A= break;=0A= }=0A= =0A= return(error);=0A= }=0A= =0A= static void=0A= bge_watchdog(ifp)=0A= struct ifnet *ifp;=0A= {=0A= struct bge_softc *sc;=0A= =0A= sc =3D ifp->if_softc;=0A= =0A= printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit);=0A= =0A= ifp->if_flags &=3D ~IFF_RUNNING;=0A= bge_init(sc);=0A= =0A= ifp->if_oerrors++;=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Stop the adapter and free any mbufs allocated to the=0A= * RX and TX lists.=0A= */=0A= static void=0A= bge_stop(sc)=0A= struct bge_softc *sc;=0A= {=0A= struct ifnet *ifp;=0A= struct ifmedia_entry *ifm;=0A= struct mii_data *mii =3D NULL;=0A= int mtmp, itmp;=0A= =0A= BGE_LOCK_ASSERT(sc);=0A= =0A= ifp =3D &sc->arpcom.ac_if;=0A= =0A= if (!sc->bge_tbi)=0A= mii =3D device_get_softc(sc->bge_miibus);=0A= =0A= callout_stop(&sc->bge_stat_ch);=0A= =0A= /*=0A= * Disable all of the receiver blocks=0A= */=0A= BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);=0A= =0A= /*=0A= * Disable all of the transmit blocks=0A= */=0A= BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);=0A= =0A= /*=0A= * Shut down all of the memory managers and related=0A= * state machines.=0A= */=0A= BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);=0A= CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);=0A= CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750) {=0A= BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);=0A= BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);=0A= }=0A= =0A= /* Disable host interrupts. */=0A= BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);=0A= CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);=0A= =0A= /*=0A= * Tell firmware we're shutting down.=0A= */=0A= BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);=0A= =0A= /* Free the RX lists. */=0A= bge_free_rx_ring_std(sc);=0A= =0A= /* Free jumbo RX list. */=0A= if (sc->bge_asicrev !=3D BGE_ASICREV_BCM5705 &&=0A= sc->bge_asicrev !=3D BGE_ASICREV_BCM5750)=0A= bge_free_rx_ring_jumbo(sc);=0A= =0A= /* Free TX buffers. */=0A= bge_free_tx_ring(sc);=0A= =0A= /*=0A= * Isolate/power down the PHY, but leave the media selection=0A= * unchanged so that things will be put back to normal when=0A= * we bring the interface back up.=0A= */=0A= if (!sc->bge_tbi) {=0A= itmp =3D ifp->if_flags;=0A= ifp->if_flags |=3D IFF_UP;=0A= ifm =3D mii->mii_media.ifm_cur;=0A= mtmp =3D ifm->ifm_media;=0A= ifm->ifm_media =3D IFM_ETHER|IFM_NONE;=0A= mii_mediachg(mii);=0A= ifm->ifm_media =3D mtmp;=0A= ifp->if_flags =3D itmp;=0A= }=0A= =0A= sc->bge_link =3D 0;=0A= =0A= sc->bge_tx_saved_considx =3D BGE_TXCONS_UNSET;=0A= =0A= ifp->if_flags &=3D ~(IFF_RUNNING | IFF_OACTIVE);=0A= =0A= return;=0A= }=0A= =0A= /*=0A= * Stop all chip I/O so that the kernel's probe routines don't=0A= * get confused by errant DMAs when rebooting.=0A= */=0A= static void=0A= bge_shutdown(dev)=0A= device_t dev;=0A= {=0A= struct bge_softc *sc;=0A= =0A= sc =3D device_get_softc(dev);=0A= =0A= BGE_LOCK(sc);=0A= bge_stop(sc);=0A= bge_reset(sc);=0A= BGE_UNLOCK(sc);=0A= =0A= return;=0A= }=0A= ------_=_NextPart_000_01C5893A.2C0FE739--
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