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From: Rafal Jaworowski <raj@FreeBSD.org>
Date: Thu, 16 Oct 2008 19:06:24 +0000 (UTC)
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Subject: svn commit: r183958 - head/sys/arm/arm
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Author: raj
Date: Thu Oct 16 19:06:24 2008
New Revision: 183958
URL: http://svn.freebsd.org/changeset/base/183958

Log:
  Eliminate flushing of L2 cache in ARM context switch routines.
  
  With VIPT L2 cache such syncing not only is redundant, but also a performance
  penalty.
  
  Pointed out by:	cognet

Modified:
  head/sys/arm/arm/swtch.S

Modified: head/sys/arm/arm/swtch.S
==============================================================================
--- head/sys/arm/arm/swtch.S	Thu Oct 16 18:09:27 2008	(r183957)
+++ head/sys/arm/arm/swtch.S	Thu Oct 16 19:06:24 2008	(r183958)
@@ -143,8 +143,6 @@ ENTRY(cpu_throw)
 	ldr	r9, .Lcpufuncs
 	mov	lr, pc
 	ldr	pc, [r9, #CF_IDCACHE_WBINV_ALL]
-	mov	lr, pc
-	ldr	pc, [r9, #CF_L2CACHE_WBINV_ALL]
 	ldr	r0, [r7, #(PCB_PL1VEC)]
 	ldr	r1, [r7, #(PCB_DACR)]
 	/*
@@ -174,8 +172,6 @@ ENTRY(cpu_throw)
 	movne	r1, #4
 	movne	lr, pc
 	ldrne	pc, [r9, #CF_DCACHE_WB_RANGE]
-	movne	lr, pc
-	ldrne	pc, [r9, #CF_L2CACHE_WB_RANGE]
 #endif /* PMAP_INCLUDE_PTE_SYNC */
 
 	/*
@@ -332,8 +328,6 @@ ENTRY(cpu_switch)
 	ldr	r1, .Lcpufuncs
 	mov	lr, pc
 	ldr	pc, [r1, #CF_IDCACHE_WBINV_ALL]
-	mov	lr, pc
-	ldr	pc, [r1, #CF_L2CACHE_WBINV_ALL]
 .Lcs_cache_purge_skipped:
 	/* rem: r6 = lock */
 	/* rem: r9 = new PCB */
@@ -366,8 +360,6 @@ ENTRY(cpu_switch)
 	mov	r1, #4
 	mov	lr, pc
 	ldr	pc, [r2, #CF_DCACHE_WB_RANGE]
-	mov	lr, pc
-	ldr	pc, [r2, #CF_L2CACHE_WB_RANGE]
 
 .Lcs_same_vector:
 #endif /* PMAP_INCLUDE_PTE_SYNC */