From owner-svn-src-all@FreeBSD.ORG Thu Jul 8 15:05:24 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 2424C106566C; Thu, 8 Jul 2010 15:05:24 +0000 (UTC) (envelope-from jchandra@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 1220D8FC14; Thu, 8 Jul 2010 15:05:24 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o68F5N5W045372; Thu, 8 Jul 2010 15:05:23 GMT (envelope-from jchandra@svn.freebsd.org) Received: (from jchandra@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o68F5NmO045365; Thu, 8 Jul 2010 15:05:23 GMT (envelope-from jchandra@svn.freebsd.org) Message-Id: <201007081505.o68F5NmO045365@svn.freebsd.org> From: "Jayachandran C." Date: Thu, 8 Jul 2010 15:05:23 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r209808 - in head/sys/mips/rmi: . dev/xlr X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jul 2010 15:05:24 -0000 Author: jchandra Date: Thu Jul 8 15:05:23 2010 New Revision: 209808 URL: http://svn.freebsd.org/changeset/base/209808 Log: 64 bit compilation support XLR platform code. Mostly changes to make casting between int and pointer and printing 64bit values safe for 32 and 64 bit compile. Approved by: rrs Modified: head/sys/mips/rmi/dev/xlr/rge.c head/sys/mips/rmi/iodi.c head/sys/mips/rmi/on_chip.c head/sys/mips/rmi/xlr_machdep.c head/sys/mips/rmi/xlr_pci.c Modified: head/sys/mips/rmi/dev/xlr/rge.c ============================================================================== --- head/sys/mips/rmi/dev/xlr/rge.c Thu Jul 8 14:59:32 2010 (r209807) +++ head/sys/mips/rmi/dev/xlr/rge.c Thu Jul 8 15:05:23 2010 (r209808) @@ -583,14 +583,14 @@ release_tx_desc(struct msgrng_msg *msg, struct mbuf *m; tx_desc = (struct p2d_tx_desc *)MIPS_PHYS_TO_KSEG0(msg->msg0); - chk_addr = (struct p2d_tx_desc *)(uint32_t) (tx_desc->frag[XLR_MAX_TX_FRAGS] & 0x00000000ffffffff); + chk_addr = (struct p2d_tx_desc *)(intptr_t)tx_desc->frag[XLR_MAX_TX_FRAGS]; if (tx_desc != chk_addr) { printf("Address %p does not match with stored addr %p - we leaked a descriptor\n", tx_desc, chk_addr); return; } if (rel_buf) { - m = (struct mbuf *)(uint32_t) (tx_desc->frag[XLR_MAX_TX_FRAGS + 1] & 0x00000000ffffffff); + m = (struct mbuf *)(intptr_t)tx_desc->frag[XLR_MAX_TX_FRAGS + 1]; m_freem(m); } free_p2d_desc(tx_desc); @@ -626,7 +626,7 @@ free_buf(vm_paddr_t paddr) (u_long)paddr, mag); return; } - m = (struct mbuf *)um; + m = (struct mbuf *)(intptr_t)um; if (m != NULL) m_freem(m); } @@ -644,9 +644,9 @@ get_buf(void) if (m_new == NULL) return NULL; - m_adj(m_new, XLR_CACHELINE_SIZE - ((unsigned int)m_new->m_data & 0x1f)); + m_adj(m_new, XLR_CACHELINE_SIZE - ((uintptr_t)m_new->m_data & 0x1f)); md = (unsigned int *)m_new->m_data; - md[0] = (unsigned int)m_new; /* Back Ptr */ + md[0] = (uintptr_t)m_new; /* Back Ptr */ md[1] = 0xf00bad; m_adj(m_new, XLR_CACHELINE_SIZE); @@ -996,7 +996,7 @@ rmi_xlr_config_pde(struct driver_data *p bucket_map |= (1ULL << bucket); } } - printf("rmi_xlr_config_pde: bucket_map=%llx\n", bucket_map); + printf("rmi_xlr_config_pde: bucket_map=%jx\n", (uintmax_t)bucket_map); /* bucket_map = 0x1; */ xlr_write_reg(priv->mmio, R_PDE_CLASS_0, (bucket_map & 0xffffffff)); @@ -1480,8 +1480,8 @@ mac_xmit(struct mbuf *m, struct rge_soft msgrng_access_disable(mflags); release_tx_desc(&msg, 0); xlr_rge_msg_snd_failed[vcpu]++; - dbg_msg("Failed packet to cpu %d, rv = %d, stid %d, msg0=%llx\n", - vcpu, rv, stid, msg.msg0); + dbg_msg("Failed packet to cpu %d, rv = %d, stid %d, msg0=%jx\n", + vcpu, rv, stid, (uintmax_t)msg.msg0); return MAC_TX_FAIL; } msgrng_access_disable(mflags); @@ -1489,7 +1489,8 @@ mac_xmit(struct mbuf *m, struct rge_soft } /* Send the packet to MAC */ - dbg_msg("Sent tx packet to stid %d, msg0=%llx, msg1=%llx \n", stid, msg.msg0, msg.msg1); + dbg_msg("Sent tx packet to stid %d, msg0=%jx, msg1=%jx \n", stid, + (uintmax_t)msg.msg0, (uintmax_t)msg.msg1); #ifdef DUMP_PACKETS { int i = 0; @@ -1638,8 +1639,8 @@ rmi_xlr_mac_msgring_handler(int bucket, int vcpu = xlr_cpu_id(); int cpu = xlr_core_id(); - dbg_msg("mac: bucket=%d, size=%d, code=%d, stid=%d, msg0=%llx msg1=%llx\n", - bucket, size, code, stid, msg->msg0, msg->msg1); + dbg_msg("mac: bucket=%d, size=%d, code=%d, stid=%d, msg0=%jx msg1=%jx\n", + bucket, size, code, stid, (uintmax_t)msg->msg0, (uintmax_t)msg->msg1); phys_addr = (uint64_t) (msg->msg0 & 0xffffffffe0ULL); length = (msg->msg0 >> 40) & 0x3fff; @@ -1670,8 +1671,8 @@ rmi_xlr_mac_msgring_handler(int bucket, return; priv = &(sc->priv); - dbg_msg("msg0 = %llx, stid = %d, port = %d, addr=%lx, length=%d, ctrl=%d\n", - msg->msg0, stid, port, addr, length, ctrl); + dbg_msg("msg0 = %jx, stid = %d, port = %d, addr=%lx, length=%d, ctrl=%d\n", + (uintmax_t)msg->msg0, stid, port, addr, length, ctrl); if (ctrl == CTRL_REG_FREE || ctrl == CTRL_JUMBO_FREE) { xlr_rge_tx_ok_done[vcpu]++; @@ -1698,8 +1699,8 @@ rmi_xlr_mac_msgring_handler(int bucket, if ((priv->frin_to_be_sent[cpu]) > MAC_FRIN_TO_BE_SENT_THRESHOLD) { mac_frin_replenish(NULL); } - dbg_msg("gmac_%d: rx packet: phys_addr = %llx, length = %x\n", - priv->instance, phys_addr, length); + dbg_msg("gmac_%d: rx packet: phys_addr = %jx, length = %x\n", + priv->instance, (uintmax_t)phys_addr, length); mac_stats_add(priv->stats.rx_packets, 1); mac_stats_add(priv->stats.rx_bytes, length); xlr_inc_counter(NETIF_RX); @@ -1887,7 +1888,7 @@ rge_attach(device_t dev) * note this is a hack to pass the irq to the iodi interrupt setup * routines */ - sc->rge_irq.__r_i = (struct resource_i *)sc->irq; + sc->rge_irq.__r_i = (struct resource_i *)(intptr_t)sc->irq; ret = bus_setup_intr(dev, &sc->rge_irq, INTR_FAST | INTR_TYPE_NET | INTR_MPSAFE, NULL, rge_intr, sc, &sc->rge_intrhand); @@ -2040,7 +2041,7 @@ rge_rx(struct rge_softc *sc, vm_paddr_t mag = xlr_paddr_lw(paddr - XLR_CACHELINE_SIZE + sizeof(uint32_t)); mips_wr_status(sr); - m = (struct mbuf *)tm; + m = (struct mbuf *)(intptr_t)tm; if (mag != 0xf00bad) { /* somebody else packet Error - FIXME in intialization */ printf("cpu %d: *ERROR* Not my packet paddr %p\n", xlr_cpu_id(), (void *)paddr); @@ -2453,7 +2454,7 @@ rmi_xlr_config_spill(xlr_reg_t * mmio, panic("Unable to allocate memory for spill area!\n"); } phys_addr = vtophys(spill); - dbg_msg("Allocate spill %d bytes at %llx\n", size, phys_addr); + dbg_msg("Allocate spill %d bytes at %jx\n", size, (uintmax_t)phys_addr); xlr_write_reg(mmio, reg_start_0, (phys_addr >> 5) & 0xffffffff); xlr_write_reg(mmio, reg_start_1, (phys_addr >> 37) & 0x07); xlr_write_reg(mmio, reg_size, spill_size); Modified: head/sys/mips/rmi/iodi.c ============================================================================== --- head/sys/mips/rmi/iodi.c Thu Jul 8 14:59:32 2010 (r209807) +++ head/sys/mips/rmi/iodi.c Thu Jul 8 15:05:23 2010 (r209808) @@ -115,7 +115,7 @@ iodi_setup_intr(device_t dev, device_t c int irq; /* This is a hack to pass in the irq */ - irq = (int)ires->__r_i; + irq = (intptr_t)ires->__r_i; if (rmi_spin_mutex_safe) mtx_lock_spin(&xlr_pic_lock); reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE); @@ -178,10 +178,10 @@ iodi_alloc_resource(device_t bus, device res->r_bustag = uart_bus_space_mem; } else if (strcmp(device_get_name(child), "ehci") == 0) { - res->r_bushandle = 0xbef24000; + res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000); res->r_bustag = rmi_pci_bus_space; } else if (strcmp(device_get_name(child), "cfi") == 0) { - res->r_bushandle = 0xbc000000; + res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000); res->r_bustag = 0; } /* res->r_start = *rid; */ Modified: head/sys/mips/rmi/on_chip.c ============================================================================== --- head/sys/mips/rmi/on_chip.c Thu Jul 8 14:59:32 2010 (r209807) +++ head/sys/mips/rmi/on_chip.c Thu Jul 8 15:05:23 2010 (r209808) @@ -210,8 +210,8 @@ xlr_msgring_handler(struct trapframe *tf if (!tx_stn_handlers[tx_stid].action) { printf("[%s]: No Handler for message from stn_id=%d, bucket=%d, " - "size=%d, msg0=%llx, dropping message\n", - __FUNCTION__, tx_stid, bucket, size, msg.msg0); + "size=%d, msg0=%jx, dropping message\n", + __FUNCTION__, tx_stid, bucket, size, (uintmax_t)msg.msg0); } else { //printf("[%s]: rx_stid = %d\n", __FUNCTION__, rx_stid); msgrng_flags_restore(mflags); Modified: head/sys/mips/rmi/xlr_machdep.c ============================================================================== --- head/sys/mips/rmi/xlr_machdep.c Thu Jul 8 14:59:32 2010 (r209807) +++ head/sys/mips/rmi/xlr_machdep.c Thu Jul 8 15:05:23 2010 (r209808) @@ -265,7 +265,6 @@ mips_init(void) init_param2(physmem); /* XXX: Catch 22. Something touches the tlb. */ - mips_cpu_init(); pmap_bootstrap(); #ifdef DDB @@ -294,13 +293,13 @@ platform_start(__register_t a0 __unused, #endif /* XXX FIXME the code below is not 64 bit clean */ /* Save boot loader and other stuff from scratch regs */ - xlr_boot1_info = *(struct boot1_info *)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0); + xlr_boot1_info = *(struct boot1_info *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0); cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1); xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2); xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3); xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4); - xlr_argv = (char **)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5); - xlr_envp = (char **)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6); + xlr_argv = (char **)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5); + xlr_envp = (char **)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6); /* TODO: Verify the magic number here */ /* FIXMELATER: xlr_boot1_info.magic_number */ @@ -387,9 +386,9 @@ platform_start(__register_t a0 __unused, * 64 bit > 4Gig and we are in 32 bit mode. */ phys_avail[j + 1] = 0xfffff000; - printf("boot map size was %llx\n", boot_map->physmem_map[i].size); + printf("boot map size was %jx\n", (intmax_t)boot_map->physmem_map[i].size); boot_map->physmem_map[i].size = phys_avail[j + 1] - phys_avail[j]; - printf("reduced to %llx\n", boot_map->physmem_map[i].size); + printf("reduced to %jx\n", (intmax_t)boot_map->physmem_map[i].size); } printf("Next segment : addr:%p -> %p \n", (void *)phys_avail[j], Modified: head/sys/mips/rmi/xlr_pci.c ============================================================================== --- head/sys/mips/rmi/xlr_pci.c Thu Jul 8 14:59:32 2010 (r209807) +++ head/sys/mips/rmi/xlr_pci.c Thu Jul 8 15:05:23 2010 (r209808) @@ -223,7 +223,7 @@ static uint32_t pci_cfg_read_32bit(uint32_t addr) { uint32_t temp = 0; - uint32_t *p = (uint32_t *) ((uint32_t) xlr_pci_config_base + (addr & ~3)); + uint32_t *p = (uint32_t *)xlr_pci_config_base + addr / sizeof(uint32_t); uint64_t cerr_cpu_log = 0; disable_and_clear_cache_error(); @@ -285,7 +285,7 @@ xlr_pcib_write_config(device_t dev, u_in data = val; } - p = (uint32_t *)((uint32_t) xlr_pci_config_base + (cfgaddr & ~3)); + p = (uint32_t *)xlr_pci_config_base + cfgaddr / sizeof(uint32_t); *p = bswap32(data); return; @@ -410,7 +410,7 @@ bridge_pcix_mask_ack(void *arg) static void bridge_pcie_ack(void *arg) { - int irq = (int)arg; + int irq = (intptr_t)arg; uint32_t reg; xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);