From owner-svn-src-head@freebsd.org Tue Jun 23 17:17:14 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 10F7E333576; Tue, 23 Jun 2020 17:17:14 +0000 (UTC) (envelope-from mhorne@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 49rtHs6lTHz3b2k; Tue, 23 Jun 2020 17:17:13 +0000 (UTC) (envelope-from mhorne@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id E2EC923EAE; Tue, 23 Jun 2020 17:17:13 +0000 (UTC) (envelope-from mhorne@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 05NHHDPn078835; Tue, 23 Jun 2020 17:17:13 GMT (envelope-from mhorne@FreeBSD.org) Received: (from mhorne@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 05NHHD5B078834; Tue, 23 Jun 2020 17:17:13 GMT (envelope-from mhorne@FreeBSD.org) Message-Id: <202006231717.05NHHD5B078834@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mhorne set sender to mhorne@FreeBSD.org using -f From: Mitchell Horne Date: Tue, 23 Jun 2020 17:17:13 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r362546 - head/share/man/man7 X-SVN-Group: head X-SVN-Commit-Author: mhorne X-SVN-Commit-Paths: head/share/man/man7 X-SVN-Commit-Revision: 362546 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.33 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Jun 2020 17:17:14 -0000 Author: mhorne Date: Tue Jun 23 17:17:13 2020 New Revision: 362546 URL: https://svnweb.freebsd.org/changeset/base/362546 Log: arch(7): small corrections for RISC-V Document that RISC-V supports multiple page sizes: 4K, 2M, and 1G. RISC-V's long double is always 128-bits wide, therefore quad precision. Mention __riscv_float_abi_soft, which can be used to differentiate between riscv64 and riscv64sf in userland code. MFC after: 3 days Modified: head/share/man/man7/arch.7 Modified: head/share/man/man7/arch.7 ============================================================================== --- head/share/man/man7/arch.7 Tue Jun 23 16:43:48 2020 (r362545) +++ head/share/man/man7/arch.7 Tue Jun 23 17:17:13 2020 (r362546) @@ -26,7 +26,7 @@ .\" .\" $FreeBSD$ .\" -.Dd March 28, 2020 +.Dd June 23, 2020 .Dt ARCH 7 .Os .Sh NAME @@ -256,8 +256,8 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta 4K .It powerpcspe Ta 4K .It powerpc64 Ta 4K -.It riscv64 Ta 4K -.It riscv64sf Ta 4K +.It riscv64 Ta 4K, 2M, 1G +.It riscv64sf Ta 4K, 2M, 1G .El .Ss Floating Point .Bl -column -offset indent "Architecture" "float, double" "long double" @@ -279,8 +279,8 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta hard Ta hard, double precision .It powerpcspe Ta hard Ta hard, double precision .It powerpc64 Ta hard Ta hard, double precision -.It riscv64 Ta hard Ta hard, double precision -.It riscv64sf Ta soft Ta soft, double precision +.It riscv64 Ta hard Ta hard, quad precision +.It riscv64sf Ta soft Ta soft, quad precision .El .Ss Default Tool Chain .Fx @@ -358,7 +358,7 @@ Architecture-specific macros: .It powerpcspe Ta Dv __powerpc__, Dv __SPE__ .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 -.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 +.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64, Dv __riscv_float_abi_soft .El .Pp Compilers may define additional variants of architecture-specific macros.