Date: Sat, 19 Jun 1999 16:55:51 -0600 From: Warner Losh <imp@harmony.village.org> To: Shaun Rowland <rowland@cis.ohio-state.edu> Cc: Marc Nicholas <marc@netstor.com>, hackers@FreeBSD.ORG Subject: Re: SMP and Celerons... Message-ID: <199906192255.QAA87149@harmony.village.org> In-Reply-To: Your message of "19 Jun 1999 15:45:54 EDT." <87k8t0c6tp.fsf@dhcp9545042.columbus.rr.com> References: <87k8t0c6tp.fsf@dhcp9545042.columbus.rr.com> <Pine.BSF.4.05.9906191302400.16699-100000@medulla.hippocampus.net>
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In message <87k8t0c6tp.fsf@dhcp9545042.columbus.rr.com> Shaun Rowland writes: : Well there is kind of. If you have a socket 370 adapter you can : un-break it. I am currently running dual Celeron 400's, and they : truly fly on this box! I can assure you it works without problems. By "broke" people mean that the celerons do not have a cache architecture that can efficiently handle SMP. So rather than getting close to a 2x (1.75) performance increase for 2 CPU, you get more like 1.5 or so due to cache coherency effects. In the MP world, this is really bad performance. It will work, but it scales poorly. I don't recall if this is due to reduce coherency functionality, or is just an artifact of cache sizes. You really want to have 1M or so of cache for CPUs in this class. Warner To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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