From owner-cvs-sys Tue Mar 21 23:03:50 1995 Return-Path: cvs-sys-owner Received: (from majordom@localhost) by freefall.cdrom.com (8.6.10/8.6.6) id XAA25125 for cvs-sys-outgoing; Tue, 21 Mar 1995 23:03:50 -0800 Received: from godzilla.zeta.org.au (godzilla.zeta.org.au [203.2.228.34]) by freefall.cdrom.com (8.6.10/8.6.6) with ESMTP id XAA25067; Tue, 21 Mar 1995 23:03:12 -0800 Received: (from bde@localhost) by godzilla.zeta.org.au (8.6.9/8.6.9) id QAA05594; Wed, 22 Mar 1995 16:58:48 +1000 Date: Wed, 22 Mar 1995 16:58:48 +1000 From: Bruce Evans Message-Id: <199503220658.QAA05594@godzilla.zeta.org.au> To: bde@zeta.org.au, phk@ref.tfs.com Subject: Re: cvs commit: src/sys/i386/isa wd.c wdreg.h Cc: CVS-commiters@freefall.cdrom.com, cvs-sys@freefall.cdrom.com, davidg@freefall.cdrom.com, rgrimes@gndrsh.aac.dev.com Sender: cvs-sys-owner@freebsd.org Precedence: bulk >Couldn't we just make a spin for a number of updates to the 1.19MHz >counter (#2 ?) for this kind of delays ? For 1.25 uS we want to >see it change twice: > n=2; > a= inb(TIMER); > while (n--) { > while (a == (b = inb(TIMER))) > ; > a = b; > } >Wouldn't that be a sensible addition to DELAY (microDELAY ?) No, it is essentially a broken form of DELAY(). First, it always does 2 inb()'s, so it always takes > 2.5uS on some buses, so it is unsuitable for use in wdwait(), where the point is that a 450nS delay is wanted and DELAY(5) was very wasteful. DELAY(n) is equivalent to DELAY(20) for n <= 20, so DELAY(1) would be no better. All these DELAYS()s do 3 inb()'s plus some bookkeeping which is fast on fast machines, so they are not much different from the above. inb(0x84) is better, but it is more likely to be too short (DELAY(1) is too long on almost all machines while DELAY(20) is too short on almost all modern machines). I couldn't get the free-running counter to work right when I rewrote DELAY(). I didn't have adequate documentation at hand. If I remember right, 8254's have a nice free-running mode but 8253's don't. I didn't calibrate DELAY() properly because it was too hard to do before clock interrupts are working and it isn't easy to handle turbo mode switches and cache effects... Bruce