Date: Sat, 19 Jun 1999 16:57:25 -0600 From: Warner Losh <imp@harmony.village.org> To: Shaun Rowland <rowland@cis.ohio-state.edu> Cc: Marc Nicholas <marc@netstor.com>, Pat Lynch <lynch@bsdunix.net>, hackers@FreeBSD.ORG Subject: Re: SMP and Celerons... Message-ID: <199906192257.QAA87169@harmony.village.org> In-Reply-To: Your message of "19 Jun 1999 15:55:36 EDT." <87hfo4c6dj.fsf@dhcp9545042.columbus.rr.com> References: <87hfo4c6dj.fsf@dhcp9545042.columbus.rr.com> <Pine.BSF.4.05.9906191302400.16699-100000@medulla.hippocampus.net> <199906191707.LAA86070@harmony.village.org>
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In message <87hfo4c6dj.fsf@dhcp9545042.columbus.rr.com> Shaun Rowland writes: : Do you mean the ones that don't have cache or the ones that have 128Kb : cache on the chip? Is there that big of a hit of the cache is on the : chip? I have seen some benchmarks and the system I have seemed to : keep up well with a dual PII 400. I don't know how well it would : scale though. By broke, I mean that they don't scale well due to cache effects. I think it may just be a size thing, but it might also be a cache coherency protocol ineffeciencies as well. The articles I've seen show that for typical workloads, people with two celerons were getting in the 1.5x range, while people with PIIs were getting 1.8x or so. Warnr To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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