Date: Tue, 8 Mar 2016 02:44:32 +0000 (UTC) From: Navdeep Parhar <np@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r296485 - in head/sys/dev/cxgbe: . common Message-ID: <201603080244.u282iWEW079801@repo.freebsd.org>
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Author: np Date: Tue Mar 8 02:44:32 2016 New Revision: 296485 URL: https://svnweb.freebsd.org/changeset/base/296485 Log: cxgbe(4): Update the interrupt handlers for hardware errors. Obtained from: Chelsio Communications Modified: head/sys/dev/cxgbe/common/common.h head/sys/dev/cxgbe/common/t4_hw.c head/sys/dev/cxgbe/t4_main.c Modified: head/sys/dev/cxgbe/common/common.h ============================================================================== --- head/sys/dev/cxgbe/common/common.h Tue Mar 8 02:34:37 2016 (r296484) +++ head/sys/dev/cxgbe/common/common.h Tue Mar 8 02:44:32 2016 (r296485) @@ -32,6 +32,9 @@ #include "t4_hw.h" +#define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \ + F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ + F_CPL_SWITCH | F_SGE | F_ULP_TX) enum { MAX_NPORTS = 4, /* max # of ports */ @@ -501,6 +504,8 @@ int t4_init_tp_params(struct adapter *ad int t4_filter_field_shift(const struct adapter *adap, int filter_sel); int t4_port_init(struct port_info *p, int mbox, int pf, int vf); void t4_fatal_err(struct adapter *adapter); +void t4_db_full(struct adapter *adapter); +void t4_db_dropped(struct adapter *adapter); int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp, int filter_index, int enable); void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp, Modified: head/sys/dev/cxgbe/common/t4_hw.c ============================================================================== --- head/sys/dev/cxgbe/common/t4_hw.c Tue Mar 8 02:34:37 2016 (r296484) +++ head/sys/dev/cxgbe/common/t4_hw.c Tue Mar 8 02:44:32 2016 (r296485) @@ -344,6 +344,43 @@ int t4_wr_mbox_meat(struct adapter *adap return -ETIMEDOUT; } +static int t4_edc_err_read(struct adapter *adap, int idx) +{ + u32 edc_ecc_err_addr_reg; + u32 edc_bist_status_rdata_reg; + + if (is_t4(adap)) { + CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); + return 0; + } + if (idx != 0 && idx != 1) { + CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); + return 0; + } + + edc_ecc_err_addr_reg = EDC_T5_REG(A_EDC_H_ECC_ERR_ADDR, idx); + edc_bist_status_rdata_reg = EDC_T5_REG(A_EDC_H_BIST_STATUS_RDATA, idx); + + CH_WARN(adap, + "edc%d err addr 0x%x: 0x%x.\n", + idx, edc_ecc_err_addr_reg, + t4_read_reg(adap, edc_ecc_err_addr_reg)); + CH_WARN(adap, + "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n", + edc_bist_status_rdata_reg, + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 8), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 16), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 24), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 32), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 40), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 48), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 56), + (unsigned long long)t4_read_reg64(adap, edc_bist_status_rdata_reg + 64)); + + return 0; +} + /** * t4_mc_read - read from MC through backdoor accesses * @adap: the adapter @@ -3867,11 +3904,14 @@ int t4_restart_aneg(struct adapter *adap return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); } +typedef void (*int_handler_t)(struct adapter *adap); + struct intr_info { - unsigned int mask; /* bits to check in interrupt status */ - const char *msg; /* message to print or NULL */ - short stat_idx; /* stat counter to increment or -1 */ - unsigned short fatal; /* whether the condition reported is fatal */ + unsigned int mask; /* bits to check in interrupt status */ + const char *msg; /* message to print or NULL */ + short stat_idx; /* stat counter to increment or -1 */ + unsigned short fatal; /* whether the condition reported is fatal */ + int_handler_t int_handler; /* platform-specific int handler */ }; /** @@ -3882,7 +3922,7 @@ struct intr_info { * * A table driven interrupt handler that applies a set of masks to an * interrupt status word and performs the corresponding actions if the - * interrupts described by the mask have occured. The actions include + * interrupts described by the mask have occurred. The actions include * optionally emitting a warning or alert message. The table is terminated * by an entry specifying mask 0. Returns the number of fatal interrupt * conditions. @@ -3899,15 +3939,17 @@ static int t4_handle_intr_status(struct continue; if (acts->fatal) { fatal++; - CH_ALERT(adapter, "%s (0x%x)\n", - acts->msg, status & acts->mask); + CH_ALERT(adapter, "%s (0x%x)\n", acts->msg, + status & acts->mask); } else if (acts->msg) - CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", - acts->msg, status & acts->mask); + CH_WARN_RATELIMIT(adapter, "%s (0x%x)\n", acts->msg, + status & acts->mask); + if (acts->int_handler) + acts->int_handler(adapter); mask |= acts->mask; } status &= mask; - if (status) /* clear processed interrupts */ + if (status) /* clear processed interrupts */ t4_write_reg(adapter, reg, status); return fatal; } @@ -3917,7 +3959,7 @@ static int t4_handle_intr_status(struct */ static void pcie_intr_handler(struct adapter *adapter) { - static struct intr_info sysbus_intr_info[] = { + static const struct intr_info sysbus_intr_info[] = { { F_RNPP, "RXNP array parity error", -1, 1 }, { F_RPCP, "RXPC array parity error", -1, 1 }, { F_RCIP, "RXCIF array parity error", -1, 1 }, @@ -3925,7 +3967,7 @@ static void pcie_intr_handler(struct ada { F_RFTP, "RXFT array parity error", -1, 1 }, { 0 } }; - static struct intr_info pcie_port_intr_info[] = { + static const struct intr_info pcie_port_intr_info[] = { { F_TPCP, "TXPC array parity error", -1, 1 }, { F_TNPP, "TXNP array parity error", -1, 1 }, { F_TFTP, "TXFT array parity error", -1, 1 }, @@ -3937,7 +3979,7 @@ static void pcie_intr_handler(struct ada { F_TDUE, "Tx uncorrectable data error", -1, 1 }, { 0 } }; - static struct intr_info pcie_intr_info[] = { + static const struct intr_info pcie_intr_info[] = { { F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 }, { F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 }, { F_MSIDATAPERR, "MSI data parity error", -1, 1 }, @@ -3972,7 +4014,7 @@ static void pcie_intr_handler(struct ada { 0 } }; - static struct intr_info t5_pcie_intr_info[] = { + static const struct intr_info t5_pcie_intr_info[] = { { F_MSTGRPPERR, "Master Response Read Queue parity error", -1, 1 }, { F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, @@ -4017,13 +4059,13 @@ static void pcie_intr_handler(struct ada if (is_t4(adapter)) fat = t4_handle_intr_status(adapter, - A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, - sysbus_intr_info) + - t4_handle_intr_status(adapter, - A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, - pcie_port_intr_info) + - t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, - pcie_intr_info); + A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, + sysbus_intr_info) + + t4_handle_intr_status(adapter, + A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, + pcie_port_intr_info) + + t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, + pcie_intr_info); else fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE, t5_pcie_intr_info); @@ -4036,7 +4078,7 @@ static void pcie_intr_handler(struct ada */ static void tp_intr_handler(struct adapter *adapter) { - static struct intr_info tp_intr_info[] = { + static const struct intr_info tp_intr_info[] = { { 0x3fffffff, "TP parity error", -1, 1 }, { F_FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, { 0 } @@ -4054,13 +4096,13 @@ static void sge_intr_handler(struct adap u64 v; u32 err; - static struct intr_info sge_intr_info[] = { + static const struct intr_info sge_intr_info[] = { { F_ERR_CPL_EXCEED_IQE_SIZE, "SGE received CPL exceeding IQE size", -1, 1 }, { F_ERR_INVALID_CIDX_INC, "SGE GTS CIDX increment too large", -1, 0 }, { F_ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, - { F_ERR_DROPPED_DB, "SGE doorbell dropped", -1, 0 }, + { F_DBFIFO_LP_INT, NULL, -1, 0, t4_db_full }, { F_ERR_DATA_CPL_ON_HIGH_QID1 | F_ERR_DATA_CPL_ON_HIGH_QID0, "SGE IQID > 1023 received CPL for FL", -1, 0 }, { F_ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, @@ -4073,23 +4115,47 @@ static void sge_intr_handler(struct adap 0 }, { F_ERR_ING_CTXT_PRIO, "SGE too many priority ingress contexts", -1, 0 }, - { F_ERR_EGR_CTXT_PRIO, - "SGE too many priority egress contexts", -1, 0 }, { F_INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, { F_EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, { 0 } }; + static const struct intr_info t4t5_sge_intr_info[] = { + { F_ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped }, + { F_DBFIFO_HP_INT, NULL, -1, 0, t4_db_full }, + { F_ERR_EGR_CTXT_PRIO, + "SGE too many priority egress contexts", -1, 0 }, + { 0 } + }; + + /* + * For now, treat below interrupts as fatal so that we disable SGE and + * get better debug */ + static const struct intr_info t6_sge_intr_info[] = { + { F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1, + "SGE PCIe error for a DBP thread", -1, 1 }, + { F_FATAL_WRE_LEN, + "SGE Actual WRE packet is less than advertized length", + -1, 1 }, + { 0 } + }; + v = (u64)t4_read_reg(adapter, A_SGE_INT_CAUSE1) | - ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); + ((u64)t4_read_reg(adapter, A_SGE_INT_CAUSE2) << 32); if (v) { CH_ALERT(adapter, "SGE parity error (%#llx)\n", - (unsigned long long)v); + (unsigned long long)v); t4_write_reg(adapter, A_SGE_INT_CAUSE1, v); t4_write_reg(adapter, A_SGE_INT_CAUSE2, v >> 32); } v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, sge_intr_info); + if (chip_id(adapter) <= CHELSIO_T5) + v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, + t4t5_sge_intr_info); + else + v |= t4_handle_intr_status(adapter, A_SGE_INT_CAUSE3, + t6_sge_intr_info); err = t4_read_reg(adapter, A_SGE_ERROR_STATS); if (err & F_ERROR_QID_VALID) { @@ -4114,7 +4180,7 @@ static void sge_intr_handler(struct adap */ static void cim_intr_handler(struct adapter *adapter) { - static struct intr_info cim_intr_info[] = { + static const struct intr_info cim_intr_info[] = { { F_PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, @@ -4124,7 +4190,7 @@ static void cim_intr_handler(struct adap { F_TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, { 0 } }; - static struct intr_info cim_upintr_info[] = { + static const struct intr_info cim_upintr_info[] = { { F_RSVDSPACEINT, "CIM reserved space access", -1, 1 }, { F_ILLTRANSINT, "CIM illegal transaction", -1, 1 }, { F_ILLWRINT, "CIM illegal write", -1, 1 }, @@ -4173,7 +4239,7 @@ static void cim_intr_handler(struct adap */ static void ulprx_intr_handler(struct adapter *adapter) { - static struct intr_info ulprx_intr_info[] = { + static const struct intr_info ulprx_intr_info[] = { { F_CAUSE_CTX_1, "ULPRX channel 1 context error", -1, 1 }, { F_CAUSE_CTX_0, "ULPRX channel 0 context error", -1, 1 }, { 0x7fffff, "ULPRX parity error", -1, 1 }, @@ -4189,7 +4255,7 @@ static void ulprx_intr_handler(struct ad */ static void ulptx_intr_handler(struct adapter *adapter) { - static struct intr_info ulptx_intr_info[] = { + static const struct intr_info ulptx_intr_info[] = { { F_PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 0 }, { F_PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, @@ -4211,7 +4277,7 @@ static void ulptx_intr_handler(struct ad */ static void pmtx_intr_handler(struct adapter *adapter) { - static struct intr_info pmtx_intr_info[] = { + static const struct intr_info pmtx_intr_info[] = { { F_PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, { F_PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, { F_PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, @@ -4234,7 +4300,7 @@ static void pmtx_intr_handler(struct ada */ static void pmrx_intr_handler(struct adapter *adapter) { - static struct intr_info pmrx_intr_info[] = { + static const struct intr_info pmrx_intr_info[] = { { F_ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, { 0x3ffff0, "PMRX framing error", -1, 1 }, { F_OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, @@ -4254,7 +4320,7 @@ static void pmrx_intr_handler(struct ada */ static void cplsw_intr_handler(struct adapter *adapter) { - static struct intr_info cplsw_intr_info[] = { + static const struct intr_info cplsw_intr_info[] = { { F_CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, { F_CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, { F_TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, @@ -4273,7 +4339,8 @@ static void cplsw_intr_handler(struct ad */ static void le_intr_handler(struct adapter *adap) { - static struct intr_info le_intr_info[] = { + unsigned int chip_ver = chip_id(adap); + static const struct intr_info le_intr_info[] = { { F_LIPMISS, "LE LIP miss", -1, 0 }, { F_LIP0, "LE 0 LIP error", -1, 0 }, { F_PARITYERR, "LE parity error", -1, 1 }, @@ -4282,7 +4349,18 @@ static void le_intr_handler(struct adapt { 0 } }; - if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, le_intr_info)) + static const struct intr_info t6_le_intr_info[] = { + { F_T6_LIPMISS, "LE LIP miss", -1, 0 }, + { F_T6_LIP0, "LE 0 LIP error", -1, 0 }, + { F_TCAMINTPERR, "LE parity error", -1, 1 }, + { F_T6_UNKNOWNCMD, "LE unknown command", -1, 1 }, + { F_SSRAMINTPERR, "LE request queue parity error", -1, 1 }, + { 0 } + }; + + if (t4_handle_intr_status(adap, A_LE_DB_INT_CAUSE, + (chip_ver <= CHELSIO_T5) ? + le_intr_info : t6_le_intr_info)) t4_fatal_err(adap); } @@ -4291,11 +4369,11 @@ static void le_intr_handler(struct adapt */ static void mps_intr_handler(struct adapter *adapter) { - static struct intr_info mps_rx_intr_info[] = { + static const struct intr_info mps_rx_intr_info[] = { { 0xffffff, "MPS Rx parity error", -1, 1 }, { 0 } }; - static struct intr_info mps_tx_intr_info[] = { + static const struct intr_info mps_tx_intr_info[] = { { V_TPFIFO(M_TPFIFO), "MPS Tx TP FIFO parity error", -1, 1 }, { F_NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, { V_TXDATAFIFO(M_TXDATAFIFO), "MPS Tx data FIFO parity error", @@ -4307,26 +4385,26 @@ static void mps_intr_handler(struct adap { F_FRMERR, "MPS Tx framing error", -1, 1 }, { 0 } }; - static struct intr_info mps_trc_intr_info[] = { + static const struct intr_info mps_trc_intr_info[] = { { V_FILTMEM(M_FILTMEM), "MPS TRC filter parity error", -1, 1 }, { V_PKTFIFO(M_PKTFIFO), "MPS TRC packet FIFO parity error", -1, 1 }, { F_MISCPERR, "MPS TRC misc parity error", -1, 1 }, { 0 } }; - static struct intr_info mps_stat_sram_intr_info[] = { + static const struct intr_info mps_stat_sram_intr_info[] = { { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 }, { 0 } }; - static struct intr_info mps_stat_tx_intr_info[] = { + static const struct intr_info mps_stat_tx_intr_info[] = { { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 }, { 0 } }; - static struct intr_info mps_stat_rx_intr_info[] = { + static const struct intr_info mps_stat_rx_intr_info[] = { { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 }, { 0 } }; - static struct intr_info mps_cls_intr_info[] = { + static const struct intr_info mps_cls_intr_info[] = { { F_MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, { F_MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, { F_HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, @@ -4351,26 +4429,27 @@ static void mps_intr_handler(struct adap mps_cls_intr_info); t4_write_reg(adapter, A_MPS_INT_CAUSE, 0); - t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ + t4_read_reg(adapter, A_MPS_INT_CAUSE); /* flush */ if (fat) t4_fatal_err(adapter); } -#define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | F_ECC_UE_INT_CAUSE) +#define MEM_INT_MASK (F_PERR_INT_CAUSE | F_ECC_CE_INT_CAUSE | \ + F_ECC_UE_INT_CAUSE) /* * EDC/MC interrupt handler. */ static void mem_intr_handler(struct adapter *adapter, int idx) { - static const char name[3][5] = { "EDC0", "EDC1", "MC" }; + static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" }; unsigned int addr, cnt_addr, v; if (idx <= MEM_EDC1) { addr = EDC_REG(A_EDC_INT_CAUSE, idx); cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx); - } else { + } else if (idx == MEM_MC) { if (is_t4(adapter)) { addr = A_MC_INT_CAUSE; cnt_addr = A_MC_ECC_STATUS; @@ -4378,22 +4457,28 @@ static void mem_intr_handler(struct adap addr = A_MC_P_INT_CAUSE; cnt_addr = A_MC_P_ECC_STATUS; } + } else { + addr = MC_REG(A_MC_P_INT_CAUSE, 1); + cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1); } v = t4_read_reg(adapter, addr) & MEM_INT_MASK; if (v & F_PERR_INT_CAUSE) - CH_ALERT(adapter, "%s FIFO parity error\n", name[idx]); + CH_ALERT(adapter, "%s FIFO parity error\n", + name[idx]); if (v & F_ECC_CE_INT_CAUSE) { u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr)); + t4_edc_err_read(adapter, idx); + t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT)); CH_WARN_RATELIMIT(adapter, "%u %s correctable ECC data error%s\n", cnt, name[idx], cnt > 1 ? "s" : ""); } if (v & F_ECC_UE_INT_CAUSE) - CH_ALERT(adapter, "%s uncorrectable ECC data error\n", - name[idx]); + CH_ALERT(adapter, + "%s uncorrectable ECC data error\n", name[idx]); t4_write_reg(adapter, addr, v); if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE)) @@ -4408,19 +4493,21 @@ static void ma_intr_handler(struct adapt u32 v, status = t4_read_reg(adapter, A_MA_INT_CAUSE); if (status & F_MEM_PERR_INT_CAUSE) { - CH_ALERT(adapter, "MA parity error, parity status %#x\n", - t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); + CH_ALERT(adapter, + "MA parity error, parity status %#x\n", + t4_read_reg(adapter, A_MA_PARITY_ERROR_STATUS1)); if (is_t5(adapter)) CH_ALERT(adapter, - "MA parity error, parity status %#x\n", - t4_read_reg(adapter, - A_MA_PARITY_ERROR_STATUS2)); + "MA parity error, parity status %#x\n", + t4_read_reg(adapter, + A_MA_PARITY_ERROR_STATUS2)); } if (status & F_MEM_WRAP_INT_CAUSE) { v = t4_read_reg(adapter, A_MA_INT_WRAP_STATUS); - CH_ALERT(adapter, "MA address wrap-around error by client %u to" - " address %#x\n", G_MEM_WRAP_CLIENT_NUM(v), - G_MEM_WRAP_ADDRESS(v) << 4); + CH_ALERT(adapter, "MA address wrap-around error by " + "client %u to address %#x\n", + G_MEM_WRAP_CLIENT_NUM(v), + G_MEM_WRAP_ADDRESS(v) << 4); } t4_write_reg(adapter, A_MA_INT_CAUSE, status); t4_fatal_err(adapter); @@ -4431,7 +4518,7 @@ static void ma_intr_handler(struct adapt */ static void smb_intr_handler(struct adapter *adap) { - static struct intr_info smb_intr_info[] = { + static const struct intr_info smb_intr_info[] = { { F_MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, { F_MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, { F_SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, @@ -4447,7 +4534,7 @@ static void smb_intr_handler(struct adap */ static void ncsi_intr_handler(struct adapter *adap) { - static struct intr_info ncsi_intr_info[] = { + static const struct intr_info ncsi_intr_info[] = { { F_CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, { F_MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, { F_TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, @@ -4472,14 +4559,17 @@ static void xgmac_intr_handler(struct ad int_cause_reg = T5_PORT_REG(port, A_MAC_PORT_INT_CAUSE); v = t4_read_reg(adap, int_cause_reg); + v &= (F_TXFIFO_PRTY_ERR | F_RXFIFO_PRTY_ERR); if (!v) return; if (v & F_TXFIFO_PRTY_ERR) - CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", port); + CH_ALERT(adap, "XGMAC %d Tx FIFO parity error\n", + port); if (v & F_RXFIFO_PRTY_ERR) - CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", port); + CH_ALERT(adap, "XGMAC %d Rx FIFO parity error\n", + port); t4_write_reg(adap, int_cause_reg, v); t4_fatal_err(adap); } @@ -4489,27 +4579,24 @@ static void xgmac_intr_handler(struct ad */ static void pl_intr_handler(struct adapter *adap) { - static struct intr_info pl_intr_info[] = { + static const struct intr_info pl_intr_info[] = { { F_FATALPERR, "Fatal parity error", -1, 1 }, { F_PERRVFID, "PL VFID_MAP parity error", -1, 1 }, { 0 } }; - static struct intr_info t5_pl_intr_info[] = { - { F_PL_BUSPERR, "PL bus parity error", -1, 1 }, + static const struct intr_info t5_pl_intr_info[] = { { F_FATALPERR, "Fatal parity error", -1, 1 }, { 0 } }; if (t4_handle_intr_status(adap, A_PL_PL_INT_CAUSE, - is_t4(adap) ? pl_intr_info : t5_pl_intr_info)) + is_t4(adap) ? + pl_intr_info : t5_pl_intr_info)) t4_fatal_err(adap); } #define PF_INTR_MASK (F_PFSW | F_PFCIM) -#define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC | F_EDC0 | \ - F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \ - F_CPL_SWITCH | F_SGE | F_ULP_TX) /** * t4_slow_intr_handler - control path interrupt handler @@ -4535,18 +4622,20 @@ int t4_slow_intr_handler(struct adapter pl_intr_handler(adapter); if (cause & F_SMB) smb_intr_handler(adapter); - if (cause & F_XGMAC0) + if (cause & F_MAC0) xgmac_intr_handler(adapter, 0); - if (cause & F_XGMAC1) + if (cause & F_MAC1) xgmac_intr_handler(adapter, 1); - if (cause & F_XGMAC_KR0) + if (cause & F_MAC2) xgmac_intr_handler(adapter, 2); - if (cause & F_XGMAC_KR1) + if (cause & F_MAC3) xgmac_intr_handler(adapter, 3); if (cause & F_PCIE) pcie_intr_handler(adapter); - if (cause & F_MC) + if (cause & F_MC0) mem_intr_handler(adapter, MEM_MC); + if (is_t5(adapter) && (cause & F_MC1)) + mem_intr_handler(adapter, MEM_MC1); if (cause & F_EDC0) mem_intr_handler(adapter, MEM_EDC0); if (cause & F_EDC1) @@ -4572,7 +4661,7 @@ int t4_slow_intr_handler(struct adapter /* Clear the interrupts just processed for which we are the master. */ t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK); - (void) t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ + (void)t4_read_reg(adapter, A_PL_INT_CAUSE); /* flush */ return 1; } @@ -4591,16 +4680,23 @@ int t4_slow_intr_handler(struct adapter */ void t4_intr_enable(struct adapter *adapter) { - u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI)); + u32 val = 0; + u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); + u32 pf = (chip_id(adapter) <= CHELSIO_T5 + ? G_SOURCEPF(whoami) + : G_T6_SOURCEPF(whoami)); + if (chip_id(adapter) <= CHELSIO_T5) + val = F_ERR_DROPPED_DB | F_ERR_EGR_CTXT_PRIO | F_DBFIFO_HP_INT; + else + val = F_ERR_PCIE_ERROR0 | F_ERR_PCIE_ERROR1 | F_FATAL_WRE_LEN; t4_write_reg(adapter, A_SGE_INT_ENABLE3, F_ERR_CPL_EXCEED_IQE_SIZE | F_ERR_INVALID_CIDX_INC | F_ERR_CPL_OPCODE_0 | - F_ERR_DROPPED_DB | F_ERR_DATA_CPL_ON_HIGH_QID1 | + F_ERR_DATA_CPL_ON_HIGH_QID1 | F_INGRESS_SIZE_ERR | F_ERR_DATA_CPL_ON_HIGH_QID0 | F_ERR_BAD_DB_PIDX3 | F_ERR_BAD_DB_PIDX2 | F_ERR_BAD_DB_PIDX1 | F_ERR_BAD_DB_PIDX0 | F_ERR_ING_CTXT_PRIO | - F_ERR_EGR_CTXT_PRIO | F_INGRESS_SIZE_ERR | - F_EGRESS_SIZE_ERR); + F_DBFIFO_LP_INT | F_EGRESS_SIZE_ERR | val); t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), PF_INTR_MASK); t4_set_reg_field(adapter, A_PL_INT_MAP0, 0, 1 << pf); } @@ -4615,7 +4711,10 @@ void t4_intr_enable(struct adapter *adap */ void t4_intr_disable(struct adapter *adapter) { - u32 pf = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI)); + u32 whoami = t4_read_reg(adapter, A_PL_WHOAMI); + u32 pf = (chip_id(adapter) <= CHELSIO_T5 + ? G_SOURCEPF(whoami) + : G_T6_SOURCEPF(whoami)); t4_write_reg(adapter, MYPF_REG(A_PL_PF_INT_ENABLE), 0); t4_set_reg_field(adapter, A_PL_INT_MAP0, 1 << pf, 0); Modified: head/sys/dev/cxgbe/t4_main.c ============================================================================== --- head/sys/dev/cxgbe/t4_main.c Tue Mar 8 02:34:37 2016 (r296484) +++ head/sys/dev/cxgbe/t4_main.c Tue Mar 8 02:44:32 2016 (r296485) @@ -8491,6 +8491,20 @@ t4_ioctl(struct cdev *dev, unsigned long return (rc); } +void +t4_db_full(struct adapter *sc) +{ + + CXGBE_UNIMPLEMENTED(__func__); +} + +void +t4_db_dropped(struct adapter *sc) +{ + + CXGBE_UNIMPLEMENTED(__func__); +} + #ifdef TCP_OFFLOAD void t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
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