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Sender: Alexander Motin <mavbsd@gmail.com>
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Date: Tue, 27 Sep 2011 20:42:42 +0300
From: Alexander Motin <mav@FreeBSD.org>
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To: Adrian Chadd <adrian@freebsd.org>
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Cc: freebsd-current@freebsd.org
Subject: Re: ath / 802.11n performance issues and timer code
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Adrian Chadd wrote:
> On 27 September 2011 23:56, Alexander Motin <mav@freebsd.org> wrote:
>>> Yes it does. x86 does the same, but with more details. The general idea
>>> of the critical section is to block context switch out of idle thread
>>> until missed time events will be handled inside cpu_activeclock().
>> I was wrong. That's not good. I have no idea about mips wait instruction
>> semantics, related to disabling interrupts. In x86 semantics proper
>> solution is:
> 
> [snip]
> 
> Why is that you've protected the halt/wait part of the idle code
> inside a critical section?
> 
> I'm not sure what to do about MIPS

Until proper solution found, try this patch. I think it should not harm:

--- machdep.c   (revision 225796)
+++ machdep.c   (working copy)
@@ -497,7 +497,8 @@
                critical_enter();
                cpu_idleclock();
        }
-       __asm __volatile ("wait");
+       if (!sched_runnable())
+               __asm __volatile ("wait");
        if (!busy) {
                cpu_activeclock();
                critical_exit();

-- 
Alexander Motin