Date: Sun, 29 Sep 1996 18:58:10 -0600 From: Steve Passe <smp@csn.net> To: erich@uruk.org Cc: freebsd-smp@freebsd.org, peter@spinner.dialix.com, terry@lambert.org Subject: Re: Generic SMP startup sequence and some docs Message-ID: <199609300058.SAA22106@clem.systemsix.com> In-Reply-To: Your message of "Sun, 29 Sep 1996 17:29:02 PDT." <199609300029.RAA29056@uruk.org>
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Hi, >One interesting detail is to note that in general, the other CPUs >are already set up for generic symmetic delivery... all you have >to do is to enable the LINTIN0 (ISA interrupts) and LINTIN1 (NMI >interrupt) entries on each CPU, as they should already be programmed. >The "local interrupt" entries of the MP Configuration Table, if >set to "0xFF" APIC destination, are already set up on all the CPUs. This is the area I am currently working on. I could use some clarification here. In this symmetric model are you using the 8259, or programming the IO APIC to handle everything? My take on this is that you program the IO APIC to replace the 8259, disable the 8259, and handle all ISA INTs thru the APIC bus, NOT the LINTIN0/1 lines. -- Steve Passe | powered by smp@csn.net | FreeBSD -----BEGIN PGP PUBLIC KEY BLOCK----- Version: 2.6.2 mQCNAzHe7tEAAAEEAM274wAEEdP+grIrV6UtBt54FB5ufifFRA5ujzflrvlF8aoE 04it5BsUPFi3jJLfvOQeydbegexspPXL6kUejYt2OeptHuroIVW5+y2M2naTwqtX WVGeBP6s2q/fPPAS+g+sNZCpVBTbuinKa/C4Q6HJ++M9AyzIq5EuvO0a8Rr9AAUR tBlTdGV2ZSBQYXNzZSA8c21wQGNzbi5uZXQ+ =ds99 -----END PGP PUBLIC KEY BLOCK-----
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