Date: Thu, 30 Mar 2000 19:08:10 +0200 (CEST) From: Bart van Leeuwen <bart@ixori.demon.nl> To: "O. Hartmann" <ohartman@ipamzlx.physik.uni-mainz.de> Cc: freebsd-smp@freebsd.org Subject: Re: SMP problems with ALR Q-SMP Message-ID: <Pine.BSF.4.21.0003301851020.60883-100000@isengard.ixori.demon.nl> In-Reply-To: <Pine.BSF.4.10.10003301458020.14969-100000@ipamzlx.physik.uni-mainz.de>
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I have no experience with this particular board so I can only say
something more general about it..
The experience I do have with SMP so far suggests that unless you have a
good reason to uncomment and change them, the NCPU, NAPIC, NBUS and NINTR
settings can be left alone as the defaults will do fine for most 'simple'
configurations.
One thing that I always wondered about, and that others may be able to
answer, is if it is a problem when the stepping level between the cpus
used in an SMP box can cause a problem. Ie, I might have an SMP board but
with only a single cpu on it right now. Lets say I bought this setup a
while back and decide to expand it with an extra cpu. Now the CPU I will
buy will be much newer and is likely from a different stepping then the
first cpu. Is there any experience with if, and how far such a setup will
work?
Processors: APIC ID Version State Family Model Step
Flags
1 0x11 BSP, usable 6 5 1
0x183fbff
0 0x11 AP, usable 6 5 0
0x183fbff
This setup works mostly fine for me (except for the problem discussed in
SMP and nv thread omn this mailing list) but it made me wonder what would
happen if the difference is bigger then in my case.... Or am I just
missing something here and seeing a non existing problem?
Bart van Leeuwen
-----------------------------------------------------------
mailto:bart@ixori.demon.nl - http://www.ixori.demon.nl/
-----------------------------------------------------------
On Thu, 30 Mar 2000, O. Hartmann wrote:
> Dear Sirs.
> I posted weeks ago about problems with a Siemens Nixdorf PCE-5Smp
> system. Well, we had problems to discover CPU configuration data
> needed for building a functioning SMP kernel and we got only HOSED
> entries.
>
> After a little search I found out that this system is originally an
> older ALR Revolution Q-SMP server. I got a new BIOS image and after
> applying this, I got "good" results with "mptable". I applyed the suggested
> entries for a custom SMP kernel, NCPU=3, NBUS=2 (EISA/PCI), NAPIC=1,NINTR=24.
> We have had some little problems with a "shot" EISA configuration and
> IRQ assignments. After obviously solving this, we compiled a new SMP kernel
> with the suggested options, but after rebooting and starting this kernel,
> the system crashes. Last message is some kind of this:
>
> AP#1 PHY#1 connot start (or similar). I do not have the whole message
> in mind. But it seems that the kernel can not start the next slave CPU.
> Single CPU kernel runs well!
>
> The machine is equipted with the following hardware: ALRa341 base board
> plus additional I/O and controller board (containing some kind of base glue
> logic and BIOS), SLOT backplane,memory card and three 100 MHz Pentium CPUs.
>
> So, reading the hardware manual says, that each CPU board comes with its
> own APIC. But as I understand this, it is only necessary to use one APIC
> to get the system running. I never tried NAPIC=3 because I should increase
> NINTR=XX upd to another value higher than 24, shouldn't I? Has anyone
> any suggestions? Is someone out here who has already configured an running
> an ALR Revolution Q-SMP under FreeBSD 4.0-STABLE? Ir would be nice if we can
> obtain some hints an tips ...
>
> Kind regards and thanks in advance,
>
> Gruss O. Hartmann
> -------------------------------------------------------------------
> ohartman@ipamzlx.physik.uni-mainz.de
>
> Klimadatenserver des IPA, Universitaet Mainz
> Netzwerk- und Systembetreuung
>
>
>
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