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From: "Randall R. Stewart" <rrs@FreeBSD.org>
To: Perforce Change Reviews <perforce@freebsd.org>
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Subject: PERFORCE change 135391 for review
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http://perforce.freebsd.org/chv.cgi?CH=135391

Change 135391 by rrs@rrs-mips2-jnpr on 2008/02/14 18:33:29

	Assure that when we hit an excpetion we DO get 
	       the right SX/UX bits set for Octeon.

Affected files ...

.. //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#15 edit

Differences ...

==== //depot/projects/mips2-jnpr/src/sys/mips/mips/exception.S#15 (text+ko) ====

@@ -59,6 +59,7 @@
 #include <machine/asm.h>
 #include <machine/cpu.h>
 #include <machine/regnum.h>
+#include <machine/cpuregs.h>
 #include <machine/pte.h>
 
 #include "assym.s"
@@ -264,6 +265,7 @@
 	mfc0    a0, COP_0_STATUS_REG    ;\
         li      a2, ~(SR_INT_ENAB | SR_EXL | SR_KSU_MASK) ;\
         and     a0, a0, a2              ;\
+	or      a0, a0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
         mtc0    a0, COP_0_STATUS_REG    
 #else
 #define CLEAR_STATUS \
@@ -471,6 +473,9 @@
 	la	gp, _C_LABEL(_gp)	# switch to kernel GP
 # Turn off fpu and enter kernel mode
 	and	t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB)
+#ifdef TARGET_OCTEON
+	or      t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX)
+#endif	
 	mtc0	t0, COP_0_STATUS_REG
 	addu	a0, k1, U_PCB_REGS
 	ITLBNOPFIX