From owner-svn-src-user@FreeBSD.ORG Tue Mar 23 01:24:24 2010 Return-Path: Delivered-To: svn-src-user@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 64AFE1065670; Tue, 23 Mar 2010 01:24:24 +0000 (UTC) (envelope-from jmallett@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 38EAB8FC12; Tue, 23 Mar 2010 01:24:24 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o2N1OO4F000785; Tue, 23 Mar 2010 01:24:24 GMT (envelope-from jmallett@svn.freebsd.org) Received: (from jmallett@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o2N1OO4H000783; Tue, 23 Mar 2010 01:24:24 GMT (envelope-from jmallett@svn.freebsd.org) Message-Id: <201003230124.o2N1OO4H000783@svn.freebsd.org> From: Juli Mallett Date: Tue, 23 Mar 2010 01:24:24 +0000 (UTC) To: src-committers@freebsd.org, svn-src-user@freebsd.org X-SVN-Group: user MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r205498 - user/jmallett/octeon/sys/mips/mips X-BeenThere: svn-src-user@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the experimental " user" src tree" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Mar 2010 01:24:24 -0000 Author: jmallett Date: Tue Mar 23 01:24:23 2010 New Revision: 205498 URL: http://svn.freebsd.org/changeset/base/205498 Log: Move to properly using REG_L/REG_S/etc. Sponsored by: Packet Forensics Modified: user/jmallett/octeon/sys/mips/mips/swtch.S Modified: user/jmallett/octeon/sys/mips/mips/swtch.S ============================================================================== --- user/jmallett/octeon/sys/mips/mips/swtch.S Tue Mar 23 01:11:10 2010 (r205497) +++ user/jmallett/octeon/sys/mips/mips/swtch.S Tue Mar 23 01:24:23 2010 (r205498) @@ -97,22 +97,6 @@ .set mips3 #endif -#if defined(ISA_MIPS32) -#define STORE sw /* 32 bit mode regsave instruction */ -#define LOAD lw /* 32 bit mode regload instruction */ -#define RSIZE 4 /* 32 bit mode register size */ -#define STORE_FP swc1 /* 32 bit mode fp regsave instruction */ -#define LOAD_FP lwc1 /* 32 bit mode fp regload instruction */ -#define FP_RSIZE 4 /* 32 bit mode fp register size */ -#else -#define STORE sd /* 64 bit mode regsave instruction */ -#define LOAD ld /* 64 bit mode regload instruction */ -#define RSIZE 8 /* 64 bit mode register size */ -#define STORE_FP sdc1 /* 64 bit mode fp regsave instruction */ -#define LOAD_FP ldc1 /* 64 bit mode fp regload instruction */ -#define FP_RSIZE 8 /* 64 bit mode fp register size */ -#endif - /* * FREEBSD_DEVELOPERS_FIXME * Some MIPS CPU may need delays using nops between executing CP0 Instructions @@ -125,28 +109,28 @@ #endif #define SAVE_U_PCB_REG(reg, offs, base) \ - STORE reg, U_PCB_REGS + (RSIZE * offs) (base) + REG_S reg, U_PCB_REGS + (SZREG * offs) (base) #define RESTORE_U_PCB_REG(reg, offs, base) \ - LOAD reg, U_PCB_REGS + (RSIZE * offs) (base) + REG_L reg, U_PCB_REGS + (SZREG * offs) (base) #define SAVE_U_PCB_FPREG(reg, offs, base) \ - STORE_FP reg, U_PCB_FPREGS + (FP_RSIZE * offs) (base) + FP_S reg, U_PCB_FPREGS + (SZFPREG * offs) (base) #define RESTORE_U_PCB_FPREG(reg, offs, base) \ - LOAD_FP reg, U_PCB_FPREGS + (FP_RSIZE * offs) (base) + FP_L reg, U_PCB_FPREGS + (SZFPREG * offs) (base) #define SAVE_U_PCB_FPSR(reg, offs, base) \ - STORE reg, U_PCB_FPREGS + (FP_RSIZE * offs) (base) + REG_S reg, U_PCB_FPREGS + (SZFPREG * offs) (base) #define RESTORE_U_PCB_FPSR(reg, offs, base) \ - LOAD reg, U_PCB_FPREGS + (FP_RSIZE * offs) (base) + REG_L reg, U_PCB_FPREGS + (SZFPREG * offs) (base) #define SAVE_U_PCB_CONTEXT(reg, offs, base) \ - STORE reg, U_PCB_CONTEXT + (RSIZE * offs) (base) + REG_S reg, U_PCB_CONTEXT + (SZREG * offs) (base) #define RESTORE_U_PCB_CONTEXT(reg, offs, base) \ - LOAD reg, U_PCB_CONTEXT + (RSIZE * offs) (base) + REG_L reg, U_PCB_CONTEXT + (SZREG * offs) (base) #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;nop;