From owner-dev-commits-src-branches@freebsd.org Fri May 28 05:51:59 2021 Return-Path: Delivered-To: dev-commits-src-branches@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id B332764C2D8; Fri, 28 May 2021 05:51:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4Frv2l4gqRz3tvp; Fri, 28 May 2021 05:51:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 7E6EE12026; Fri, 28 May 2021 05:51:59 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.16.1/8.16.1) with ESMTP id 14S5pxZJ014765; Fri, 28 May 2021 05:51:59 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.16.1/8.16.1/Submit) id 14S5pxBa014764; Fri, 28 May 2021 05:51:59 GMT (envelope-from git) Date: Fri, 28 May 2021 05:51:59 GMT Message-Id: <202105280551.14S5pxBa014764@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org From: Kevin Bowling Subject: git: 166ad86c33ba - stable/12 - e1000: Rework em_msi_link interrupt filter MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: kbowling X-Git-Repository: src X-Git-Refname: refs/heads/stable/12 X-Git-Reftype: branch X-Git-Commit: 166ad86c33ba4ca1a1b235913a9ae553ebf6a425 Auto-Submitted: auto-generated X-BeenThere: dev-commits-src-branches@freebsd.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Commits to the stable branches of the FreeBSD src repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 May 2021 05:51:59 -0000 The branch stable/12 has been updated by kbowling (ports committer): URL: https://cgit.FreeBSD.org/src/commit/?id=166ad86c33ba4ca1a1b235913a9ae553ebf6a425 commit 166ad86c33ba4ca1a1b235913a9ae553ebf6a425 Author: Kevin Bowling AuthorDate: 2021-04-25 08:22:23 +0000 Commit: Kevin Bowling CommitDate: 2021-05-28 05:51:46 +0000 e1000: Rework em_msi_link interrupt filter * Fix 82574 Link Status Changes, carrying the OTHER mask bit around as needed. * Move igb-class LSC re-arming out of FAST back into the handler. * Clarify spurious/other interrupt re-arms in FAST. In MSI-X mode, 82574 and igb-class devices use an interrupt filter to handle Link Status Changes. We want to do LSC re-arms in the handler to take advantage of autoclear (EIAC) single shot behavior. 82574 uses 'Other' in ICR and IMS for LSC interrupt types when in MSI-X mode, so we need to set and re-arm the 'Other' bit during attach and after ICR reads in the FAST handler if not an LSC or after handling on LSC due to autoclearing. This work was primarily done to address the referenced PR, but inspired some clarification and improvement for igb-class devices once the intentions of previous bug fix attempts became clearer. PR: 211219 Reported by: Alexey Tested by: kbowling (I210 lagg), markj (I210) Approved by: markj MFC after: 1 month Differential Revision: https://reviews.freebsd.org/D29943 (cherry picked from commit eea55de7b10808b86277d7fdbed2d05d3c6db1b2) --- sys/dev/e1000/if_em.c | 41 ++++++++++++++++++++++++----------------- sys/dev/e1000/if_em.h | 2 -- 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/sys/dev/e1000/if_em.c b/sys/dev/e1000/if_em.c index f284de275066..819ae802e654 100644 --- a/sys/dev/e1000/if_em.c +++ b/sys/dev/e1000/if_em.c @@ -1508,6 +1508,7 @@ em_msix_link(void *arg) { struct adapter *adapter = arg; u32 reg_icr; + bool notlink = false; ++adapter->link_irq; MPASS(adapter->hw.back != NULL); @@ -1516,15 +1517,19 @@ em_msix_link(void *arg) if (reg_icr & E1000_ICR_RXO) adapter->rx_overruns++; - if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { + if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) em_handle_link(adapter->ctx); - } else if (adapter->hw.mac.type == e1000_82574) { - /* Only re-arm 82574 if em_if_update_admin_status() won't. */ - E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | - E1000_IMS_LSC); - } + else + notlink = true; - if (adapter->hw.mac.type == e1000_82574) { + /* Re-arm for other/spurious interrupts */ + if (notlink && adapter->hw.mac.type >= igb_mac_min) { + E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); + E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); + } else if (adapter->hw.mac.type == e1000_82574) { + if (notlink) + E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC | + E1000_IMS_OTHER); /* * Because we must read the ICR for this interrupt it may * clear other causes using autoclear, for this reason we @@ -1532,10 +1537,6 @@ em_msix_link(void *arg) */ if (reg_icr) E1000_WRITE_REG(&adapter->hw, E1000_ICS, adapter->ims); - } else { - /* Re-arm unconditionally */ - E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); - E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); } return (FILTER_HANDLED); @@ -1872,10 +1873,13 @@ em_if_update_admin_status(if_ctx_t ctx) if (hw->mac.type < em_mac_min) lem_smartspeed(adapter); - else if (hw->mac.type == e1000_82574 && + else if (hw->mac.type >= igb_mac_min && + adapter->intr_type == IFLIB_INTR_MSIX) { + E1000_WRITE_REG(&adapter->hw, E1000_IMS, E1000_IMS_LSC); + E1000_WRITE_REG(&adapter->hw, E1000_EIMS, adapter->link_mask); + } else if (hw->mac.type == e1000_82574 && adapter->intr_type == IFLIB_INTR_MSIX) - E1000_WRITE_REG(&adapter->hw, E1000_IMS, EM_MSIX_LINK | - E1000_IMS_LSC); + E1000_WRITE_REG(hw, E1000_IMS, E1000_IMS_LSC | E1000_IMS_OTHER); } static void @@ -2087,7 +2091,10 @@ em_if_msix_intr_assign(if_ctx_t ctx, int msix) if (adapter->hw.mac.type < igb_mac_min) { adapter->ivars |= (8 | rx_vectors) << 16; adapter->ivars |= 0x80000000; + /* Enable the "Other" interrupt type for link status change */ + adapter->ims |= E1000_IMS_OTHER; } + return (0); fail: iflib_irq_free(ctx, &adapter->irq); @@ -3476,8 +3483,8 @@ em_if_intr_enable(if_ctx_t ctx) struct e1000_hw *hw = &adapter->hw; u32 ims_mask = IMS_ENABLE_MASK; - if (hw->mac.type == e1000_82574) { - E1000_WRITE_REG(hw, EM_EIAC, EM_MSIX_MASK); + if (adapter->intr_type == IFLIB_INTR_MSIX) { + E1000_WRITE_REG(hw, EM_EIAC, adapter->ims); ims_mask |= adapter->ims; } E1000_WRITE_REG(hw, E1000_IMS, ims_mask); @@ -3489,7 +3496,7 @@ em_if_intr_disable(if_ctx_t ctx) struct adapter *adapter = iflib_get_softc(ctx); struct e1000_hw *hw = &adapter->hw; - if (hw->mac.type == e1000_82574) + if (adapter->intr_type == IFLIB_INTR_MSIX) E1000_WRITE_REG(hw, EM_EIAC, 0); E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); } diff --git a/sys/dev/e1000/if_em.h b/sys/dev/e1000/if_em.h index efad9251105b..7ef97274191b 100644 --- a/sys/dev/e1000/if_em.h +++ b/sys/dev/e1000/if_em.h @@ -342,8 +342,6 @@ #define EM_VFTA_SIZE 128 #define EM_TSO_SIZE 65535 #define EM_TSO_SEG_SIZE 4096 /* Max dma segment size */ -#define EM_MSIX_MASK 0x01F00000 /* For 82574 use */ -#define EM_MSIX_LINK 0x01000000 /* For 82574 use */ #define ETH_ZLEN 60 #define ETH_ADDR_LEN 6 #define EM_CSUM_OFFLOAD (CSUM_IP | CSUM_IP_UDP | CSUM_IP_TCP) /* Offload bits in mbuf flag */