From owner-freebsd-questions@FreeBSD.ORG Tue Nov 9 19:52:06 2010 Return-Path: Delivered-To: freebsd-questions@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 3EF091065673 for ; Tue, 9 Nov 2010 19:52:06 +0000 (UTC) (envelope-from cswiger@mac.com) Received: from asmtpout025.mac.com (asmtpout025.mac.com [17.148.16.100]) by mx1.freebsd.org (Postfix) with ESMTP id 240678FC1C for ; Tue, 9 Nov 2010 19:52:06 +0000 (UTC) MIME-version: 1.0 Content-transfer-encoding: 7BIT Content-type: text/plain; charset=us-ascii Received: from cswiger1.apple.com ([17.209.4.71]) by asmtp025.mac.com (Sun Java(tm) System Messaging Server 6.3-7.04 (built Sep 26 2008; 64bit)) with ESMTPSA id <0LBM00F5OV6SIC00@asmtp025.mac.com> for freebsd-questions@freebsd.org; Tue, 09 Nov 2010 11:52:05 -0800 (PST) X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 ipscore=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx engine=6.0.2-1004200000 definitions=main-1011090121 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.2.15,1.0.148,0.0.0000 definitions=2010-11-09_12:2010-11-09, 2010-11-09, 1970-01-01 signatures=0 From: Chuck Swiger In-reply-to: Date: Tue, 09 Nov 2010 11:52:04 -0800 Message-id: References: <201011091256.51140.naylor.b.david@gmail.com> <4CD949D7.6030003@stillbilde.net> To: David Brodbeck X-Mailer: Apple Mail (2.1082) Cc: freebsd-questions@freebsd.org Subject: Re: Per core frequency control X-BeenThere: freebsd-questions@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: User questions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Nov 2010 19:52:06 -0000 On Nov 9, 2010, at 9:54 AM, David Brodbeck wrote: > On Tue, Nov 9, 2010 at 5:17 AM, Svein Skogen (Listmail account) > wrote: >> You did read the "symmetric" part of "symmetric multi processor" didn't you? >> >> It's a limitation of the technology. One clock. > > I don't think that's quite true. The newer Intel server chipsets have > the ability to throttle back idle cores and boost the speed of active > ones, to improve performance on single-threaded workloads. You're talking about: http://en.wikipedia.org/wiki/Intel_Turbo_Boost In point of fact, what this is doing is that the CPU is adjusting it's own multipliers of Bclk (normally 133.33 MHz, although 160MHz can also used if XMP profile timing is active) if it can halt or put to sleep some of the cores into C1/C1E/C3 states. There still is only one base clock frequency being provided to all of the cores, and the ones which are still awake will still all be running at the same speed. [1] Regards, -- -Chuck [1] Modulo extreme thermal conditions involving TM1 but not TM2; TM1 thresholds are per-CPU.