From nobody Wed Mar 25 04:46:54 2026 X-Original-To: dev-commits-src-main@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4fgZBQ2v6gz6WhRj for ; Wed, 25 Mar 2026 04:46:54 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R12" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4fgZBQ2Lhmz3mMb for ; Wed, 25 Mar 2026 04:46:54 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1774414014; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=3Ru1U4ZRA72SGVN/XP7ci55eHIO2WCDDj9RtsI78LAc=; b=fE6HJd9GERFMN9rxgP/CWoQI9n03FjSrYqaqSDui9WpVMH+ts3L65XcqGw4rq3aAiiTPqY AyPYEgK0sVyKEL9i639GqRP8FcJ1qtadV1FA8ocYNwZUMsmOzdwhkam7tHTHXZH6pk5TQp ijk+UBqm61CTbsWSZ8BjZkL1Pw78BK8LrivCygYIyO3JJ9cOj2v+7kSjM/7r55OWHlk2Mg 5qSfKdriNqC/TiZDSQESo5tVclsIAdMOVo+Rhuhv1gvC7lmPLt7f4Ue6UF3ETqVo3YJu/J /bL8i1RWGBhpJuyLeUlNMod6RT3bU9na5DQjt9IMJroc4IfdamIrPZOlj+IHZg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1774414014; a=rsa-sha256; cv=none; b=F7DGZFKbGfOtaxYGboCR+t6KkEfvFNRM2R7HScMwNPUHSfuHNrH+bUy3zyma3sydVtb4/m PfXRwl6WdnvuAoyYC3ImBVixAciCdiGHlIK53wS5Dh0/yFeqJiX6YZZaN7rq5QE9IaF2JD Ea4e1fK9VW3YmBWK/I42ng6AwBoQp8C1acFJ+JNBocw2v8qrRPs/D3xSA0VqOaFW4wnfq5 x5Pw3WB8HsXxAtgytYAEk3BnJcaF6kk8hooyGUQpEfgWNFNjycIhMz+LAlPBJYM0IChHxI 0jujzykGYpXzBQDpBAHTvKuYCyPTIKuMjuPQSNCGOxvUZEGfUk0+ULbldPuEvg== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1774414014; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=3Ru1U4ZRA72SGVN/XP7ci55eHIO2WCDDj9RtsI78LAc=; b=t0TIf9Zk/OoR/pX3n56nsJ3zzJpwdsejCTaJwLFpTa3iscYDqlRkOM8AdnKYnT5h1ZazQt Mj9dsS+W2sIzvicfWSVG5o2ql1LtfBv7T/79XDcZCwuyOjiUnlknXV6vJAaJq2JyabxJkg QQ8eLMaRcioPNCnKw+1evEoh0ITdvJuyZCgGknS9flIlY4Y/UPsweNy7Qy5i6U/wR1tQuw wJ2uJG/axHmg7uJV0k+XOZfOQ7QZy3wm7fM1MGowvyAgLRHQ05N7ebUujN2LehSK+x2Tdw ND2BNfbD/LNidFFoZpYUOdaobDlM4f9+plKXSuVhEftaCsmWR2XCOmxP9LbGMQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4fgZBQ1X8mzqgc for ; Wed, 25 Mar 2026 04:46:54 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 36bbe by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Wed, 25 Mar 2026 04:46:54 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Jaeyoon Choi Subject: git: c4386988baa2 - main - ufshci: fix bug in ufshci_req_sdb_enable List-Id: Commit messages for the main branch of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-main List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-main@freebsd.org Sender: owner-dev-commits-src-main@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: jaeyoon X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: c4386988baa2ecdcb482c8ccace183dc643d097c Auto-Submitted: auto-generated Date: Wed, 25 Mar 2026 04:46:54 +0000 Message-Id: <69c368be.36bbe.6582e4ba@gitrepo.freebsd.org> The branch main has been updated by jaeyoon: URL: https://cgit.FreeBSD.org/src/commit/?id=c4386988baa2ecdcb482c8ccace183dc643d097c commit c4386988baa2ecdcb482c8ccace183dc643d097c Author: Jaeyoon Choi AuthorDate: 2026-03-24 05:12:14 +0000 Commit: Jaeyoon Choi CommitDate: 2026-03-24 16:45:27 +0000 ufshci: fix bug in ufshci_req_sdb_enable When enabling the request queue, safely reset the list base address. This was added due to a quirk in the Qualcomm UFS controller during the process of activating it. Sponsored by: Samsung Electronics Reviewed by: imp (mentor) Differential Revision: https://reviews.freebsd.org/D55984 --- sys/dev/ufshci/ufshci_req_sdb.c | 40 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/sys/dev/ufshci/ufshci_req_sdb.c b/sys/dev/ufshci/ufshci_req_sdb.c index ca47aa159c5b..54542f48b32c 100644 --- a/sys/dev/ufshci/ufshci_req_sdb.c +++ b/sys/dev/ufshci/ufshci_req_sdb.c @@ -374,34 +374,63 @@ ufshci_req_sdb_enable(struct ufshci_controller *ctrlr, struct ufshci_req_queue *req_queue) { struct ufshci_hw_queue *hwq = &req_queue->hwq[UFSHCI_SDB_Q]; + int error = 0; + + mtx_lock(&hwq->recovery_lock); + mtx_lock(&hwq->qlock); if (req_queue->is_task_mgmt) { uint32_t hcs, utmrldbr, utmrlrsr; + uint32_t utmrlba, utmrlbau; + + /* + * Some controllers require re-enabling. When a controller is + * re-enabled, the utmrlba registers are initialized, and these + * must be reconfigured upon re-enabling. + */ + utmrlba = hwq->req_queue_addr & 0xffffffff; + utmrlbau = hwq->req_queue_addr >> 32; + ufshci_mmio_write_4(ctrlr, utmrlba, utmrlba); + ufshci_mmio_write_4(ctrlr, utmrlbau, utmrlbau); hcs = ufshci_mmio_read_4(ctrlr, hcs); if (!(hcs & UFSHCIM(UFSHCI_HCS_REG_UTMRLRDY))) { ufshci_printf(ctrlr, "UTP task management request list is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utmrldbr = ufshci_mmio_read_4(ctrlr, utmrldbr); if (utmrldbr != 0) { ufshci_printf(ctrlr, "UTP task management request list door bell is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utmrlrsr = UFSHCIM(UFSHCI_UTMRLRSR_REG_UTMRLRSR); ufshci_mmio_write_4(ctrlr, utmrlrsr, utmrlrsr); } else { uint32_t hcs, utrldbr, utrlcnr, utrlrsr; + uint32_t utrlba, utrlbau; + + /* + * Some controllers require re-enabling. When a controller is + * re-enabled, the utrlba registers are initialized, and these + * must be reconfigured upon re-enabling. + */ + utrlba = hwq->req_queue_addr & 0xffffffff; + utrlbau = hwq->req_queue_addr >> 32; + ufshci_mmio_write_4(ctrlr, utrlba, utrlba); + ufshci_mmio_write_4(ctrlr, utrlbau, utrlbau); hcs = ufshci_mmio_read_4(ctrlr, hcs); if (!(hcs & UFSHCIM(UFSHCI_HCS_REG_UTRLRDY))) { ufshci_printf(ctrlr, "UTP transfer request list is not ready\n"); - return (ENXIO); + error = ENXIO; + goto out; } utrldbr = ufshci_mmio_read_4(ctrlr, utrldbr); @@ -434,7 +463,10 @@ ufshci_req_sdb_enable(struct ufshci_controller *ctrlr, hwq->recovery_state = RECOVERY_NONE; - return (0); +out: + mtx_unlock(&hwq->qlock); + mtx_unlock(&hwq->recovery_lock); + return (error); } int