From nobody Fri Jul 10 15:28:26 2026 X-Original-To: dev-commits-src-branches@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4gxbMH0Zlcz6lJ6D for ; Fri, 10 Jul 2026 15:28:27 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "YR1" (not verified)) by mx1.freebsd.org (Postfix) with ESMTPS id 4gxbMG58DCz442H for ; Fri, 10 Jul 2026 15:28:26 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1783697306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=WWWk3yYOhHsjpZnhvYEWKSrjqvToQdz3/+l8+fbyn3g=; b=vpnqktpuj4tX2ULAx2yvqzhJ6YlcVGrJ9HEqxTPaUgFnOdsgf0h8sriy9/5ANklTEk5Dnz Y59SSnvDASU6bMHt8XkoVzHK/SP03ZTmna5J4mDsO+90xxljhhHss0qUJqAX8UBXkXvIu4 xMV9ALSzyVXDICaJqpOn4VfH3SlMDEeTzKldtcDuILLGFoGSWhjq914tEGMEgSgt2GwfyU KudPq8TvYudBIy9tJyDfWaglwi6mlEaVLIiepTmlQC7kKE380bYIKVS3v0AJZalqc0QH/l hNJNNOenN9BGgiYUQticw2f2IWoC8BxSarzYn9x9MrlRzmgTjwcc6znKWMbi6Q== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1783697306; a=rsa-sha256; cv=none; b=UyjL9J/G/YWumpJ86qdr4a4Ko+cqPbOB9WU1NZrUlnPRzOgt6xKD1IJCaEYmfo5ZotBudW r87CX8cRTxKFjPQFY5+7TLSOfk7RZdGvuxRcQzeAih59FFOV0ceC+YsBUfc9ZYZTEADXr9 +mtl2TfSsxWvRI3ucyt3cKM3ftFL0+FF6gUu+RXhl68NuUNim58MXnSpsGNi4f6/6v0axN e+Xu7z1CwG/OkuZTebq7Ym01zCZ2uR1YV+R2IUqH2Pn1WjubYY+bf2rA4UKi/A9V+gqCia LE/LUSIKA8u0P0tUybb+AzS6a/43qZOKgKKcnclzfzWGakxyLo84ObgI9g0r4Q== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1783697306; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=WWWk3yYOhHsjpZnhvYEWKSrjqvToQdz3/+l8+fbyn3g=; b=s1CluquwMBlyzc1ESSRfno/g0LxbdaCFYZXBU+sZwxW979VfAMpE7U+Um7ERSsHft2iHKe sqBhhFK4nGok7MEbeQPu8Q5a09XRzYqk+/R6FxAUJXffVhpBcPD2oSSN0QfnhHRY6lqWR9 Kb7A5rMfcEnCA81tlW16SyhRGV6JgpHXdRktq+mHiszPVXFEDJEHLW3zSLaWOvbJW+3+em Mbm/TSj6ROMQi6hRUivDELCriWkYBLjRUOPyEHOMYoL7wptqfqa3xMKaBJEQp3nFmwEuLI R7idQfyYJEU9mbuIw7dUkI83ctI/5nOt4koH4nGXRtiz6PlY4Wq8ynU/kPFY5Q== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) by mxrelay.nyi.freebsd.org (Postfix) with ESMTP id 4gxbMG3yYnz10Tp for ; Fri, 10 Jul 2026 15:28:26 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from git (uid 1279) (envelope-from git@FreeBSD.org) id 324ad by gitrepo.freebsd.org (DragonFly Mail Agent v0.13+ on gitrepo.freebsd.org); Fri, 10 Jul 2026 15:28:26 +0000 To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Cc: Paulo Fragoso From: Mitchell Horne Subject: git: 067755c74a3d - stable/15 - hwpmc_amd: fix amd_get_msr() MSR offset for newer counter bases List-Id: Commits to the stable branches of the FreeBSD src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-branches List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-branches@freebsd.org Sender: owner-dev-commits-src-branches@FreeBSD.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: mhorne X-Git-Repository: src X-Git-Refname: refs/heads/stable/15 X-Git-Reftype: branch X-Git-Commit: 067755c74a3dafd669b92963d4ad3ee1fcaa790e Auto-Submitted: auto-generated Date: Fri, 10 Jul 2026 15:28:26 +0000 Message-Id: <6a510f9a.324ad.4b0031d8@gitrepo.freebsd.org> The branch stable/15 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=067755c74a3dafd669b92963d4ad3ee1fcaa790e commit 067755c74a3dafd669b92963d4ad3ee1fcaa790e Author: Paulo Fragoso AuthorDate: 2026-03-12 15:21:33 +0000 Commit: Mitchell Horne CommitDate: 2026-07-10 15:28:08 +0000 hwpmc_amd: fix amd_get_msr() MSR offset for newer counter bases The previous code subtracted AMD_PMC_PERFCTR_0 (0xC0010004) from all perfctr MSR addresses to compute a relative offset. This is incorrect for counters using AMD_PMC_CORE_BASE (0xC0010200), AMD_PMC_L3_BASE (0xC0010230), and AMD_PMC_DF_BASE (0xC0010240), producing wrong offsets. Fix by promoting amd_core_npmcs, amd_l3_npmcs, and amd_df_npmcs to static module-level variables and computing the correct flat RDPMC index per AMD BKDG 24594 page 440: ECX 0-5: Core counters 0-5 ECX 6-9: DF counters 0-3 ECX 10-15: L3 Cache counters 0-5 ECX 16-27: DF counters 4-15 ECX > 27: Reserved, returns EINVAL Reviewed by: Ali Mashtizadeh , mhorne Sponsored by: NLINK (https://nlink.com.br), Recife, Brazil Fixes: 37bba2ad92d8 ("hwpmc_amd: Add support for additional counters") Differential Revision: https://reviews.freebsd.org/D55607 (cherry picked from commit ce9aff829e02c9a21c04eae77a45f2193d1ed5a1) --- sys/dev/hwpmc/hwpmc_amd.c | 36 +++++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/sys/dev/hwpmc/hwpmc_amd.c b/sys/dev/hwpmc/hwpmc_amd.c index b34cbffcffa8..c174502caefb 100644 --- a/sys/dev/hwpmc/hwpmc_amd.c +++ b/sys/dev/hwpmc/hwpmc_amd.c @@ -60,8 +60,8 @@ struct amd_descr { }; static int amd_npmcs; +static int amd_core_npmcs, amd_l3_npmcs, amd_df_npmcs; static struct amd_descr amd_pmcdesc[AMD_NPMCS_MAX]; - struct amd_event_code_map { enum pmc_event pe_ev; /* enum value */ uint16_t pe_code; /* encoded event mask */ @@ -659,10 +659,41 @@ amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) static int amd_get_msr(int ri, uint32_t *msr) { + int df_idx; + KASSERT(ri >= 0 && ri < amd_npmcs, ("[amd,%d] ri %d out of range", __LINE__, ri)); - *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; + /* + * Map counter row index to RDPMC ECX value. + * + * AMD BKDG 24594 rev 3.37, page 440, + * "RDPMC Read Performance-Monitoring Counter": + * ECX 0-5: Core counters 0-5 + * ECX 6-9: DF/Northbridge counters 0-3 + * ECX 10-15: L3 Cache counters 0-5 + * ECX 16-27: DF/Northbridge counters 4-15 + * + * AMD PPR 57930-A0 section 2.1.9, + * "Register Sharing" for DF counter details. + */ + if (ri < amd_core_npmcs) { + /* ECX 0-5: Core counters */ + *msr = ri; + } else if (ri < amd_core_npmcs + amd_l3_npmcs) { + /* ECX 10-15: L3 Cache counters */ + *msr = 10 + (ri - amd_core_npmcs); + } else { + /* ECX 6-9: DF counters 0-3 + * ECX 16-27: DF counters 4-15 */ + df_idx = ri - amd_core_npmcs - amd_l3_npmcs; + if (df_idx < 4) + *msr = 6 + df_idx; + else if (df_idx < 16) + *msr = 16 + (df_idx - 4); + else + return (EINVAL); + } return (0); } @@ -762,7 +793,6 @@ pmc_amd_initialize(void) enum pmc_cputype cputype; int error, i, ncpus; int family, model, stepping; - int amd_core_npmcs, amd_l3_npmcs, amd_df_npmcs; struct amd_descr *d; /*