Date: Sun, 19 Mar 1995 10:27:19 -0800 From: "Russell L. Carter" <rcarter@geli.com> To: dufault@hda.com, rgrimes@gndrsh.aac.dev.com Cc: hackers@freefall.cdrom.com Subject: Re: SMP work Message-ID: <199503191827.KAA13613@geli.clusternet>
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|From: "Rodney W. Grimes" <rgrimes@gndrsh.aac.dev.com> |Subject: Re: SMP work |To: dufault@hda.com (Peter Dufault) |Date: Sat, 18 Mar 1995 14:06:04 -0800 (PST) |Cc: hackers@freefall.cdrom.com | |> |> Rodney W. Grimes writes: |> > |> > [CC: trimmed] |> > ... | |> (Intel licenced Alliant's Concurrency Control Unit for future |> generations of the i860 - yeah, right. Are they continuing that |> with their "merchant" MP?) Are you referring to the unisys project? My understanding was that was a pentium project, not i860. | |I have no idea what they did with the i860 and Alliants stuff, so |I can not say if they are continuing that. Somehow I doubt it |very much since the iX60 group is over in the SuperComputer division, |which is more like a seperate company. | Intel SSD sells "MP" nodes with 2 i860s, and by all accounts it works fine under OS1/AD. But some codes I've benchmarked in support of a proposal show that 2 P590 cpus (running FreeBSD :) are roughly equal to 8 MP nodes. If you think about the economics and price/performance a little bit, one starts to be a wee bit astounded. (There's a lot more to it, but the upshot is that these are production USAF codes that run on Paragons daily). Anyway, I'm real interested in the dual cpu stuff, it would be a pretty neat thing to have, though we'd have to see whether it could be made efficient enough to make sense. Is there not much interest in a simple master/slave kernel with dual run queues.? That would work very well for parallel numerical algorithms, and I believe it's the way the Paragon is run. The book by Schimmel makes it look not all that hard, easy to say from the bleachers, I guess. Russell |-- |Rod Grimes rgrimes@gndrsh.aac.dev.com |Accurate Automation Company Custom computers for FreeBSD | |
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