Date: Tue, 26 Jul 2011 10:50:34 +0000 (UTC) From: "Jayachandran C." <jchandra@FreeBSD.org> To: src-committers@freebsd.org, svn-src-user@freebsd.org Subject: svn commit: r224415 - in user/jchandra/mips-xlp-support/sys/mips: conf nlm Message-ID: <201107261050.p6QAoYjL004660@svn.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: jchandra Date: Tue Jul 26 10:50:33 2011 New Revision: 224415 URL: http://svn.freebsd.org/changeset/base/224415 Log: PCI - Support PCIe devices Add swapping bus space for PCIe devices, update xlp_pci.c to use it for PCIe devices. Also minor clean up in xlp_pci.c Added: user/jchandra/mips-xlp-support/sys/mips/nlm/bus_space_rmi_pci.c Modified: user/jchandra/mips-xlp-support/sys/mips/conf/XLP64 user/jchandra/mips-xlp-support/sys/mips/nlm/files.xlp user/jchandra/mips-xlp-support/sys/mips/nlm/xlp_pci.c Modified: user/jchandra/mips-xlp-support/sys/mips/conf/XLP64 ============================================================================== --- user/jchandra/mips-xlp-support/sys/mips/conf/XLP64 Tue Jul 26 04:33:00 2011 (r224414) +++ user/jchandra/mips-xlp-support/sys/mips/conf/XLP64 Tue Jul 26 10:50:33 2011 (r224415) @@ -21,7 +21,7 @@ machine mips mips64eb ident XLP64 options ISA_MIPS64 -makeoptions ARCH_FLAGS="-march=mips64 -mabi=64" +makeoptions ARCH_FLAGS="-march=mips64r2 -mabi=64" makeoptions KERNLOADADDR=0xffffffff80100000 include "../nlm/std.xlp" @@ -93,7 +93,9 @@ device uart device pci # Network +device miibus device ether +device msk device da device scbus Added: user/jchandra/mips-xlp-support/sys/mips/nlm/bus_space_rmi_pci.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ user/jchandra/mips-xlp-support/sys/mips/nlm/bus_space_rmi_pci.c Tue Jul 26 10:50:33 2011 (r224415) @@ -0,0 +1,768 @@ +/*- + * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights + * reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGE. + * + * NETLOGIC_BSD */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD: head/sys/mips/rmi/bus_space_rmi_pci.c 204175 2010-02-21 17:27:20Z rrs $"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> +#include <sys/endian.h> +#include <sys/malloc.h> +#include <sys/ktr.h> + +#include <vm/vm.h> +#include <vm/pmap.h> +#include <vm/vm_kern.h> +#include <vm/vm_extern.h> + +#include <machine/bus.h> +#include <machine/cache.h> + +static int +rmi_pci_bus_space_map(void *t, bus_addr_t addr, + bus_size_t size, int flags, + bus_space_handle_t * bshp); + +static void +rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh, + bus_size_t size); + +static int +rmi_pci_bus_space_subregion(void *t, + bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size, + bus_space_handle_t * nbshp); + +static u_int8_t +rmi_pci_bus_space_read_1(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static u_int16_t +rmi_pci_bus_space_read_2(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static u_int32_t +rmi_pci_bus_space_read_4(void *t, + bus_space_handle_t handle, + bus_size_t offset); + +static void +rmi_pci_bus_space_read_multi_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_1(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t value); + +static void +rmi_pci_bus_space_write_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t value); + +static void +rmi_pci_bus_space_write_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t value); + +static void +rmi_pci_bus_space_write_multi_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + + +static void +rmi_pci_bus_space_set_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, + size_t count); +static void +rmi_pci_bus_space_set_region_4(void *t, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, + size_t count); + +static void +rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, + bus_size_t offset __unused, bus_size_t len __unused, int flags); + +static void +rmi_pci_bus_space_copy_region_2(void *t, + bus_space_handle_t bsh1, + bus_size_t off1, + bus_space_handle_t bsh2, + bus_size_t off2, size_t count); + +u_int8_t +rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset); + +static u_int16_t +rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset); + +static u_int32_t +rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset); +static void +rmi_pci_bus_space_read_multi_stream_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_stream_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_read_multi_stream_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, + size_t count); + +void +rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value); +static void +rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value); + +static void +rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value); + +static void +rmi_pci_bus_space_write_multi_stream_1(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int8_t * addr, + size_t count); +static void +rmi_pci_bus_space_write_multi_stream_2(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int16_t * addr, + size_t count); + +static void +rmi_pci_bus_space_write_multi_stream_4(void *t, + bus_space_handle_t handle, + bus_size_t offset, + const u_int32_t * addr, + size_t count); + +#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__) + +static struct bus_space local_rmi_pci_bus_space = { + /* cookie */ + (void *)0, + + /* mapping/unmapping */ + rmi_pci_bus_space_map, + rmi_pci_bus_space_unmap, + rmi_pci_bus_space_subregion, + + /* allocation/deallocation */ + NULL, + NULL, + + /* barrier */ + rmi_pci_bus_space_barrier, + + /* read (single) */ + rmi_pci_bus_space_read_1, + rmi_pci_bus_space_read_2, + rmi_pci_bus_space_read_4, + NULL, + + /* read multiple */ + rmi_pci_bus_space_read_multi_1, + rmi_pci_bus_space_read_multi_2, + rmi_pci_bus_space_read_multi_4, + NULL, + + /* read region */ + rmi_pci_bus_space_read_region_1, + rmi_pci_bus_space_read_region_2, + rmi_pci_bus_space_read_region_4, + NULL, + + /* write (single) */ + rmi_pci_bus_space_write_1, + rmi_pci_bus_space_write_2, + rmi_pci_bus_space_write_4, + NULL, + + /* write multiple */ + rmi_pci_bus_space_write_multi_1, + rmi_pci_bus_space_write_multi_2, + rmi_pci_bus_space_write_multi_4, + NULL, + + /* write region */ + NULL, + rmi_pci_bus_space_write_region_2, + rmi_pci_bus_space_write_region_4, + NULL, + + /* set multiple */ + NULL, + NULL, + NULL, + NULL, + + /* set region */ + NULL, + rmi_pci_bus_space_set_region_2, + rmi_pci_bus_space_set_region_4, + NULL, + + /* copy */ + NULL, + rmi_pci_bus_space_copy_region_2, + NULL, + NULL, + + /* read (single) stream */ + rmi_pci_bus_space_read_stream_1, + rmi_pci_bus_space_read_stream_2, + rmi_pci_bus_space_read_stream_4, + NULL, + + /* read multiple stream */ + rmi_pci_bus_space_read_multi_stream_1, + rmi_pci_bus_space_read_multi_stream_2, + rmi_pci_bus_space_read_multi_stream_4, + NULL, + + /* read region stream */ + rmi_pci_bus_space_read_region_1, + rmi_pci_bus_space_read_region_2, + rmi_pci_bus_space_read_region_4, + NULL, + + /* write (single) stream */ + rmi_pci_bus_space_write_stream_1, + rmi_pci_bus_space_write_stream_2, + rmi_pci_bus_space_write_stream_4, + NULL, + + /* write multiple stream */ + rmi_pci_bus_space_write_multi_stream_1, + rmi_pci_bus_space_write_multi_stream_2, + rmi_pci_bus_space_write_multi_stream_4, + NULL, + + /* write region stream */ + NULL, + rmi_pci_bus_space_write_region_2, + rmi_pci_bus_space_write_region_4, + NULL, +}; + +/* generic bus_space tag */ +bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space; + +/* + * Map a region of device bus space into CPU virtual address space. + */ +static int +rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr, + bus_size_t size __unused, int flags __unused, + bus_space_handle_t * bshp) +{ + *bshp = addr; + return (0); +} + +/* + * Unmap a region of device bus space. + */ +static void +rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused, + bus_size_t size __unused) +{ +} + +/* + * Get a new handle for a subregion of an already-mapped area of bus space. + */ + +static int +rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size __unused, + bus_space_handle_t * nbshp) +{ + *nbshp = bsh + offset; + return (0); +} + +/* + * Read a 1, 2, 4, or 8 byte quantity from bus space + * described by tag/handle/offset. + */ + +static u_int8_t +rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + return (u_int8_t) (*(volatile u_int8_t *)(handle + offset)); +} + +static u_int16_t +rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + u_int16_t value; + + value = *(volatile u_int16_t *)(handle + offset); + return bswap16(value); +} + +static u_int32_t +rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle, + bus_size_t offset) +{ + uint32_t value; + + value = *(volatile u_int32_t *)(handle + offset); + return bswap32(value); +} + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle/offset and copy into buffer provided. + */ +static void +rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + while (count--) { + *addr = *(volatile u_int8_t *)(handle + offset); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + + while (count--) { + *addr = *(volatile u_int16_t *)(handle + offset); + *addr = bswap16(*addr); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + + while (count--) { + *addr = *(volatile u_int32_t *)(handle + offset); + *addr = bswap32(*addr); + addr++; + } +} + +/* + * Write the 1, 2, 4, or 8 byte value `value' to bus space + * described by tag/handle/offset. + */ + +static void +rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t value) +{ + mips_sync(); + *(volatile u_int8_t *)(handle + offset) = value; +} + +static void +rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value) +{ + mips_sync(); + *(volatile u_int16_t *)(handle + offset) = bswap16(value); +} + + +static void +rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value) +{ + mips_sync(); + *(volatile u_int32_t *)(handle + offset) = bswap32(value); +} + +/* + * Write `count' 1, 2, 4, or 8 byte quantities from the buffer + * provided to bus space described by tag/handle/offset. + */ + + +static void +rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int8_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int8_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int16_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr); + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr); + addr++; + } +} + +/* + * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described + * by tag/handle starting at `offset'. + */ + +static void +rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 2) + (*(volatile u_int16_t *)(addr)) = value; +} + +static void +rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value, size_t count) +{ + bus_addr_t addr = bsh + offset; + + for (; count != 0; count--, addr += 4) + (*(volatile u_int32_t *)(addr)) = value; +} + + +/* + * Copy `count' 1, 2, 4, or 8 byte values from bus space starting + * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. + */ +static void +rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, + bus_size_t off1, bus_space_handle_t bsh2, + bus_size_t off2, size_t count) +{ + TODO(); +} + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle/offset and copy into buffer provided. + */ + +u_int8_t +rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + + return *((volatile u_int8_t *)(handle + offset)); +} + + +static u_int16_t +rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + return *(volatile u_int16_t *)(handle + offset); +} + + +static u_int32_t +rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset) +{ + return (*(volatile u_int32_t *)(handle + offset)); +} + + +static void +rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int8_t *)(handle + offset)); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int16_t *)(handle + offset)); + addr++; + } +} + +static void +rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + while (count--) { + *addr = (*(volatile u_int32_t *)(handle + offset)); + addr++; + } +} + + + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle and starting at `offset' and copy into + * buffer provided. + */ +void +rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int8_t *)(baddr)); + baddr += 1; + } +} + +void +rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int16_t *)(baddr)); + baddr += 2; + } +} + +void +rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + *addr++ = (*(volatile u_int32_t *)(baddr)); + baddr += 4; + } +} + + +void +rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int8_t value) +{ + mips_sync(); + *(volatile u_int8_t *)(handle + offset) = value; +} + +static void +rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int16_t value) +{ + mips_sync(); + *(volatile u_int16_t *)(handle + offset) = value; +} + + +static void +rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, + bus_size_t offset, u_int32_t value) +{ + mips_sync(); + *(volatile u_int32_t *)(handle + offset) = value; +} + + +static void +rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int8_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int8_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int16_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int16_t *)(handle + offset)) = *addr; + addr++; + } +} + +static void +rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + mips_sync(); + while (count--) { + (*(volatile u_int32_t *)(handle + offset)) = *addr; + addr++; + } +} + +void +rmi_pci_bus_space_write_region_2(void *t, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t * addr, + size_t count) +{ + bus_addr_t baddr = (bus_addr_t) bsh + offset; + + while (count--) { + (*(volatile u_int16_t *)(baddr)) = *addr; + addr++; + baddr += 2; + } +} + +void +rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh, + bus_size_t offset, const u_int32_t * addr, size_t count) +{ + bus_addr_t baddr = bsh + offset; + + while (count--) { + (*(volatile u_int32_t *)(baddr)) = *addr; + addr++; + baddr += 4; + } +} + +static void +rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, + bus_size_t offset __unused, bus_size_t len __unused, int flags) +{ + +} Modified: user/jchandra/mips-xlp-support/sys/mips/nlm/files.xlp ============================================================================== --- user/jchandra/mips-xlp-support/sys/mips/nlm/files.xlp Tue Jul 26 04:33:00 2011 (r224414) +++ user/jchandra/mips-xlp-support/sys/mips/nlm/files.xlp Tue Jul 26 10:50:33 2011 (r224415) @@ -6,6 +6,7 @@ mips/nlm/tick.c standard mips/nlm/board.c standard mips/nlm/cms.c standard mips/nlm/bus_space_rmi.c standard +mips/nlm/bus_space_rmi_pci.c standard mips/nlm/mpreset.S standard mips/nlm/xlp_pci.c optional pci mips/nlm/intern_dev.c optional pci Modified: user/jchandra/mips-xlp-support/sys/mips/nlm/xlp_pci.c ============================================================================== --- user/jchandra/mips-xlp-support/sys/mips/nlm/xlp_pci.c Tue Jul 26 04:33:00 2011 (r224414) +++ user/jchandra/mips-xlp-support/sys/mips/nlm/xlp_pci.c Tue Jul 26 10:50:33 2011 (r224415) @@ -84,7 +84,7 @@ xlp_pci_init_resources(void) panic("pci_init_resources irq_rman"); port_rman.rm_start = 0; - port_rman.rm_end = ~0u; + port_rman.rm_end = ~0ul; port_rman.rm_type = RMAN_ARRAY; port_rman.rm_descr = "I/O ports"; if (rman_init(&port_rman) @@ -92,7 +92,7 @@ xlp_pci_init_resources(void) panic("pci_init_resources port_rman"); mem_rman.rm_start = 0; - mem_rman.rm_end = ~0u; + mem_rman.rm_end = ~0ul; mem_rman.rm_type = RMAN_ARRAY; mem_rman.rm_descr = "I/O memory"; if (rman_init(&mem_rman) @@ -100,7 +100,7 @@ xlp_pci_init_resources(void) panic("pci_init_resources mem_rman"); emul_rman.rm_start = 0; - emul_rman.rm_end = ~0u; + emul_rman.rm_end = ~0ul; emul_rman.rm_type = RMAN_ARRAY; emul_rman.rm_descr = "Emulated MEMIO"; if (rman_init(&emul_rman) @@ -443,9 +443,7 @@ mips_platform_pci_setup_intr(device_t de xlp_establish_intr(device_get_name(child), filt, intr, arg, xlpirq, flags, cookiep, extra_ack); -// return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr, -// arg, cookiep)); - return 0; + return (0); } static int @@ -459,15 +457,16 @@ mips_platform_pci_teardown_intr(device_t return (bus_generic_teardown_intr(dev, child, irq, cookie)); } -static vm_offset_t +static void assign_soc_resource(device_t child, int type, u_long *startp, u_long *endp, - u_long *countp) + u_long *countp, struct rman **rm, vm_offset_t *va) { int devid = pci_get_device(child); int inst = pci_get_function(child); int node = pci_get_slot(child) / 8; - vm_offset_t va = 0; + *rm = NULL; + *va = 0; switch (devid) { case PCI_DEVICE_ID_NLM_UART: switch (type) { @@ -476,9 +475,10 @@ assign_soc_resource(device_t child, int *countp = 1; break; case SYS_RES_MEMORY: - va = nlm_regbase_uart(node, inst) + XLP_IO_PCI_HDRSZ; + *va = nlm_regbase_uart(node, inst) + XLP_IO_PCI_HDRSZ; *startp = MIPS_KSEG1_TO_PHYS(va); *countp = 0x100; + *rm = &emul_rman; break; }; break; @@ -496,8 +496,6 @@ assign_soc_resource(device_t child, int } break; } - - return (va); } static struct resource * @@ -517,11 +515,9 @@ xlp_pci_alloc_resource(device_t bus, dev */ if (pci_get_bus(child) == 0 && pci_get_vendor(child) == PCI_VENDOR_NETLOGIC) - va = assign_soc_resource(child, type, &start, &end, - &count); - if (va) - rm = &emul_rman; - else + assign_soc_resource(child, type, &start, &end, + &count, &rm, &va); + if (rm == NULL) { switch (type) { case SYS_RES_IRQ: rm = &irq_rman; @@ -537,6 +533,7 @@ xlp_pci_alloc_resource(device_t bus, dev default: return (0); + } } rv = rman_reserve_resource(rm, start, end, count, flags, child); @@ -550,7 +547,12 @@ xlp_pci_alloc_resource(device_t bus, dev va = (vm_offset_t)pmap_mapdev(start, count); rman_set_bushandle(rv, va); rman_set_virtual(rv, (void *)va); - rman_set_bustag(rv, rmi_bus_space); + + /* SoC devices don't need swap */ + if (pci_get_bus(child) != 0) + rman_set_bustag(rv, rmi_pci_bus_space); + else + rman_set_bustag(rv, rmi_bus_space); } if (needactivate) {
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201107261050.p6QAoYjL004660>