From owner-svn-src-head@freebsd.org Wed Feb 15 23:49:29 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BFFCECE0443; Wed, 15 Feb 2017 23:49:29 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 80C0BE90; Wed, 15 Feb 2017 23:49:29 +0000 (UTC) (envelope-from imp@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v1FNnSwm001505; Wed, 15 Feb 2017 23:49:28 GMT (envelope-from imp@FreeBSD.org) Received: (from imp@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v1FNnS4Q001503; Wed, 15 Feb 2017 23:49:28 GMT (envelope-from imp@FreeBSD.org) Message-Id: <201702152349.v1FNnS4Q001503@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: imp set sender to imp@FreeBSD.org using -f From: Warner Losh Date: Wed, 15 Feb 2017 23:49:28 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r313785 - in head/sys/dev: acpica pci X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Feb 2017 23:49:29 -0000 Author: imp Date: Wed Feb 15 23:49:28 2017 New Revision: 313785 URL: https://svnweb.freebsd.org/changeset/base/313785 Log: Use symbolic constants for OSC support / control negotiations. Differential Revision: https://reviews.freebsd.org/D9604 Modified: head/sys/dev/acpica/acpi_pcib_acpi.c head/sys/dev/pci/pcireg.h Modified: head/sys/dev/acpica/acpi_pcib_acpi.c ============================================================================== --- head/sys/dev/acpica/acpi_pcib_acpi.c Wed Feb 15 23:33:14 2017 (r313784) +++ head/sys/dev/acpica/acpi_pcib_acpi.c Wed Feb 15 23:49:28 2017 (r313785) @@ -309,15 +309,19 @@ acpi_pcib_osc(struct acpi_hpcib_softc *s 0x96, 0x57, 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66 }; + /* Status Field */ + cap_set[PCI_OSC_STATUS] = 0; + /* Support Field: Extended PCI Config Space, MSI */ - cap_set[1] = 0x11; + cap_set[PCI_OSC_SUPPORT] = PCIM_OSC_SUPPORT_EXT_PCI_CONF | + PCIM_OSC_SUPPORT_MSI; /* Control Field */ - cap_set[2] = 0; + cap_set[PCI_OSC_CTL] = 0; #ifdef PCI_HP /* Control Field: PCI Express Native Hot Plug */ - cap_set[2] |= 0x1; + cap_set[PCI_OSC_CTL] |= PCIM_OSC_CTL_PCIE_HP; #endif status = acpi_EvaluateOSC(sc->ap_handle, pci_host_bridge_uuid, 1, @@ -330,10 +334,16 @@ acpi_pcib_osc(struct acpi_hpcib_softc *s return; } - if (cap_set[0] != 0) { + if (cap_set[PCI_OSC_STATUS] != 0) { device_printf(sc->ap_dev, "_OSC returned error %#x\n", cap_set[0]); } + +#ifdef PCI_HP + if ((cap_set[PCI_OSC_CTL] & PCIM_OSC_CTL_PCIE_HP) == 0 && bootverbose) { + device_printf(sc->ap_dev, "_OSC didn't allow HP control\n"); + } +#endif } static int Modified: head/sys/dev/pci/pcireg.h ============================================================================== --- head/sys/dev/pci/pcireg.h Wed Feb 15 23:33:14 2017 (r313784) +++ head/sys/dev/pci/pcireg.h Wed Feb 15 23:49:28 2017 (r313785) @@ -1040,3 +1040,19 @@ #define PCIR_SRIOV_BARS 0x24 #define PCIR_SRIOV_BAR(x) (PCIR_SRIOV_BARS + (x) * 4) +/* + * PCI Express Firmware Interface definitions + */ +#define PCI_OSC_STATUS 0 +#define PCI_OSC_SUPPORT 1 +#define PCIM_OSC_SUPPORT_EXT_PCI_CONF 0x01 /* Extended PCI Config Space */ +#define PCIM_OSC_SUPPORT_ASPM 0x02 /* Active State Power Management */ +#define PCIM_OSC_SUPPORT_CPMC 0x04 /* Clock Power Management Cap */ +#define PCIM_OSC_SUPPORT_SEG_GROUP 0x08 /* PCI Segment Groups supported */ +#define PCIM_OSC_SUPPORT_MSI 0x10 /* MSI signalling supported */ +#define PCI_OSC_CTL 2 +#define PCIM_OSC_CTL_PCIE_HP 0x01 /* PCIe Native Hot Plug */ +#define PCIM_OSC_CTL_SHPC_HP 0x02 /* SHPC Native Hot Plug */ +#define PCIM_OSC_CTL_PCIE_PME 0x04 /* PCIe Native Power Mgt Events */ +#define PCIM_OSC_CTL_PCIE_AER 0x08 /* PCIe Advanced Error Reporting */ +#define PCIM_OSC_CTL_PCIE_CAP_STRUCT 0x10 /* Various Capability Structures */