Date: Mon, 3 Feb 1997 09:34:35 +0000 (GMT) From: Alan Cox <alan@cymru.net> To: smp@csn.net (Steve Passe) Cc: terry@lambert.org, davem@jenolan.rutgers.edu, michaelh@cet.co.jp, netdev@roxanne.nuclecu.unam.mx, roque@di.fc.ul.pt, freebsd-smp@FreeBSD.org, smpdev@roxanne.nuclecu.unam.mx Subject: Re: SMP Message-ID: <199702030934.JAA14489@snowcrash.cymru.net> In-Reply-To: <199702030003.RAA11312@clem.systemsix.com> from "Steve Passe" at Feb 2, 97 05:03:18 pm
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> I don't have a clue. I was under the belief that we have a MESI compliant > board to deal with, but I could easily be wrong about that. You do have a MESI compliant board. > Cache coherency is provided by the features of the P5/P6 chips and > whatever MB glue their specifications require in an MP board. > > The Intel MP spec gives this only lip service. See the > MP spec, ver 1.4, sections 3.3: External Cache SubSystem and appendix > B.6: Other IPI Applications, for details. The spec can be found at: The bus state and timing diagrams for this are in the pentium pro hardware manual. Basically on a read from the other processors cache the processor with the dirty data holds the reader off and writes the modified data back sets its state to shared and then lets the other cpu continue. Alan
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