From owner-svn-src-head@freebsd.org Wed Aug 19 20:31:36 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id CB3759BED47; Wed, 19 Aug 2015 20:31:36 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id BBEBF12B9; Wed, 19 Aug 2015 20:31:36 +0000 (UTC) (envelope-from ian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.70]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id t7JKVaAL028512; Wed, 19 Aug 2015 20:31:36 GMT (envelope-from ian@FreeBSD.org) Received: (from ian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id t7JKVaaC028510; Wed, 19 Aug 2015 20:31:36 GMT (envelope-from ian@FreeBSD.org) Message-Id: <201508192031.t7JKVaaC028510@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: ian set sender to ian@FreeBSD.org using -f From: Ian Lepore Date: Wed, 19 Aug 2015 20:31:36 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r286942 - head/sys/arm/freescale/imx X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Aug 2015 20:31:37 -0000 Author: ian Date: Wed Aug 19 20:31:35 2015 New Revision: 286942 URL: https://svnweb.freebsd.org/changeset/base/286942 Log: Add compatible strings for all the hardware this driver works with. Also, move the READ/WRITE bus space access macros from the header into the source file, and rename them to RD2/WR2 to make it clear they're 16-bit accessors. (READ/WRITE just don't seem like good names to be in a public header file.) Modified: head/sys/arm/freescale/imx/imx_wdog.c head/sys/arm/freescale/imx/imx_wdogreg.h Modified: head/sys/arm/freescale/imx/imx_wdog.c ============================================================================== --- head/sys/arm/freescale/imx/imx_wdog.c Wed Aug 19 20:31:03 2015 (r286941) +++ head/sys/arm/freescale/imx/imx_wdog.c Wed Aug 19 20:31:35 2015 (r286942) @@ -65,6 +65,20 @@ static struct resource_spec imx_wdog_spe { -1, 0 } }; +static struct ofw_compat_data compat_data[] = { + {"fsl,imx6sx-wdt", 1}, + {"fsl,imx6sl-wdt", 1}, + {"fsl,imx6q-wdt", 1}, + {"fsl,imx53-wdt", 1}, + {"fsl,imx51-wdt", 1}, + {"fsl,imx50-wdt", 1}, + {"fsl,imx35-wdt", 1}, + {"fsl,imx27-wdt", 1}, + {"fsl,imx25-wdt", 1}, + {"fsl,imx21-wdt", 1}, + {NULL, 0} +}; + static void imx_watchdog(void *, u_int, int *); static int imx_wdog_probe(device_t); static int imx_wdog_attach(device_t); @@ -83,6 +97,10 @@ static driver_t imx_wdog_driver = { static devclass_t imx_wdog_devclass; DRIVER_MODULE(imx_wdog, simplebus, imx_wdog_driver, imx_wdog_devclass, 0, 0); +#define RD2(_sc, _r) \ + bus_space_read_2((_sc)->sc_bst, (_sc)->sc_bsh, (_r)) +#define WR2(_sc, _r, _v) \ + bus_space_write_2((_sc)->sc_bst, (_sc)->sc_bsh, (_r), (_v)) static void imx_watchdog(void *arg, u_int cmd, int *error) @@ -95,8 +113,8 @@ imx_watchdog(void *arg, u_int cmd, int * mtx_lock(&sc->sc_mtx); /* Refresh counter, since we feels good */ - WRITE(sc, WDOG_SR_REG, WDOG_SR_STEP1); - WRITE(sc, WDOG_SR_REG, WDOG_SR_STEP2); + WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1); + WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2); /* We don't require precession, so "-10" (/1024) is ok */ timeout = (1 << ((cmd & WD_INTERVAL) - 10)) / 1000000; @@ -105,14 +123,14 @@ imx_watchdog(void *arg, u_int cmd, int * device_printf(sc->sc_dev, "WARNING: watchdog can't be disabled!!!"); sc->sc_timeout = timeout; - reg = READ(sc, WDOG_CR_REG); + reg = RD2(sc, WDOG_CR_REG); reg &= ~WDOG_CR_WT_MASK; reg |= (timeout << (WDOG_CR_WT_SHIFT + 1)) & WDOG_CR_WT_MASK; - WRITE(sc, WDOG_CR_REG, reg); + WR2(sc, WDOG_CR_REG, reg); /* Refresh counter */ - WRITE(sc, WDOG_SR_REG, WDOG_SR_STEP1); - WRITE(sc, WDOG_SR_REG, WDOG_SR_STEP2); + WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1); + WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2); *error = 0; } else { *error = EOPNOTSUPP; @@ -132,11 +150,10 @@ imx_wdog_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "fsl,imx51-wdt") && - !ofw_bus_is_compatible(dev, "fsl,imx53-wdt")) + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); - device_set_desc(dev, "Freescale i.MX5xx Watchdog Timer"); + device_set_desc(dev, "Freescale i.MX Watchdog"); return (0); } Modified: head/sys/arm/freescale/imx/imx_wdogreg.h ============================================================================== --- head/sys/arm/freescale/imx/imx_wdogreg.h Wed Aug 19 20:31:03 2015 (r286941) +++ head/sys/arm/freescale/imx/imx_wdogreg.h Wed Aug 19 20:31:35 2015 (r286942) @@ -59,7 +59,3 @@ #define WDOG_MCR_REG 0x08 /* Miscellaneous Control Register */ #define WDOG_MCR_PDE (1 << 0) -#define READ(_sc, _r) \ - bus_space_read_2((_sc)->sc_bst, (_sc)->sc_bsh, (_r)) -#define WRITE(_sc, _r, _v) \ - bus_space_write_2((_sc)->sc_bst, (_sc)->sc_bsh, (_r), (_v))