From owner-freebsd-sparc64@FreeBSD.ORG  Thu May 29 11:14:27 2003
Return-Path: <owner-freebsd-sparc64@FreeBSD.ORG>
Delivered-To: freebsd-sparc64@freebsd.org
Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125])
	by hub.freebsd.org (Postfix) with ESMTP id 4762137B401
	for <freebsd-sparc64@FreeBSD.org>;
	Thu, 29 May 2003 11:14:27 -0700 (PDT)
Received: from prisma.quccc.org (c7057.upc-c.chello.nl [212.187.7.57])
	by mx1.FreeBSD.org (Postfix) with ESMTP id 621EA43FA3
	for <freebsd-sparc64@FreeBSD.org>;
	Thu, 29 May 2003 11:14:24 -0700 (PDT)
	(envelope-from einekoai@chello.nl)
Received: from [192.168.1.13] (unknown [192.168.1.13])
	by prisma.quccc.org (Postfix) with ESMTP
	id CDAD93C; Thu, 29 May 2003 20:14:24 +0200 (CEST)
From: Koop Mast <einekoai@chello.nl>
To: Thomas Moestl <t.moestl@tu-bs.de>
In-Reply-To: <20030529113731.GB630@crow.dom2ip.de>
References: <20030529113731.GB630@crow.dom2ip.de>
Content-Type: text/plain
Message-Id: <1054232211.310.8.camel@healthy.prisma.quccc.org>
Mime-Version: 1.0
X-Mailer: Ximian Evolution 1.3.92 (Preview Release)
Date: 29 May 2003 20:16:52 +0200
Content-Transfer-Encoding: 7bit
cc: freebsd-sparc64@FreeBSD.org
Subject: Re: PLEASE TEST: interrupt assignment patch
X-BeenThere: freebsd-sparc64@freebsd.org
X-Mailman-Version: 2.1.1
Precedence: list
List-Id: Porting FreeBSD to the Sparc <freebsd-sparc64.freebsd.org>
List-Unsubscribe: <http://lists.freebsd.org/mailman/listinfo/freebsd-sparc64>,
	<mailto:freebsd-sparc64-request@freebsd.org?subject=unsubscribe>
List-Archive: <http://lists.freebsd.org/pipermail/freebsd-sparc64>
List-Post: <mailto:freebsd-sparc64@freebsd.org>
List-Help: <mailto:freebsd-sparc64-request@freebsd.org?subject=help>
List-Subscribe: <http://lists.freebsd.org/mailman/listinfo/freebsd-sparc64>,
	<mailto:freebsd-sparc64-request@freebsd.org?subject=subscribe>
X-List-Received-Date: Thu, 29 May 2003 18:14:27 -0000

Op do 29-05-2003, om 13:37 schreef Thomas Moestl:
> Hi,
> 
> I would like to get the attached patch into 5.1; although I am quite
> confident that it will not break anything, we need a good test coverage
> (i.e. testing on many different models) to make sure this is the case,
> since we are that close to a release.
> 
> Therefore, I would very much appreciate if people could give this a
> spin on their machines and report back.
> 
> The aim of the patch is to fix the interrupt assignment on e450s; it
> should not have any effect on other boxen. It has been tested so far
> on two e450s, a Blade 100 and an u60.
> 
> Thanks,
> 	- Thomas

On a Ultra 10 
cpu0: Sun Microsystems UltraSparc-IIi Processor (440.00 MHz CPU)
Only diff is in the dmesg:

-pcib0: Sabre, impl 0, version 0, ign 0x7c0
+pcib0: Sabre, impl 0, version 0, ign 0x7c0, bus A

-Koop