Date: Mon, 14 Nov 2011 15:35:33 -0600 From: John Veit <John_Veit@DELL.com> To: John Baldwin <jhb@freebsd.org>, "freebsd-acpi@freebsd.org" <freebsd-acpi@freebsd.org> Cc: Don Croft <Don_Croft@Dell.com> Subject: RE: Sandy Bridge Support for FBSD 8.1 Message-ID: <975552A94CBC0F4DA60ED7B36C949CBA03D0849EB5@shandy.Beer.Town> In-Reply-To: <201111141606.52981.jhb@freebsd.org> References: <975552A94CBC0F4DA60ED7B36C949CBA03D08496A8@shandy.Beer.Town> <201111141606.52981.jhb@freebsd.org>
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The Intel SandyBridge_EDS volume 2 decribes how the CPUBUS0, CPUBUS1 values= are accessed for each physical CPU Slot. The BIOS loads these values at bo= ot time. For SandyBridge each physical CPU has multiple PCI segments for in= tegrated IO and CPU devices. Thus when 2 CPU's are present the following va= lues are set: CPU0BUS0=3D0 (IIO, PCH), CPU0BUS1=3D63 (IMC, DMA, etc),=20 CPU1BUS0=3D64, CPU1BUS1=3D127. Note: We are using amd64 build of FBSD 8.1. It looks like the qpi driver is= not supported for Sandy Bridge. =20 -----Original Message----- From: John Baldwin [mailto:jhb@freebsd.org]=20 Sent: Monday, November 14, 2011 3:07 PM To: freebsd-acpi@freebsd.org Cc: John Veit; Don Croft Subject: Re: Sandy Bridge Support for FBSD 8.1 On Monday, November 14, 2011 9:50:14 am John Veit wrote: > Motherboard: Dell R720 with 2 SandyBridge X6 CPU's I do not see some=20 > devices on the second CPU slot (e.g. the Integrated Memory Controller devices @ bus(127):slot(15):fn(0)). I do see the IMC devices on = the first CPU Slot (bus(63):slot(15):fn(0)), however. >=20 > Please advise. > Thanks, John Veit > jveit@dell.com Eh. How are you seeing those devices in the first place? My understanding= is that these devices showed up on busses starting with bus 255 on down. = This is managed by the qpi driver in sys/x86/pci/qpi.c. Hmm, it doesn't se= e any devices on my SB desktop machine here. Ah. It does a CPU ID check t= hat needs to be updated. However, are the buses defined to be 127 and 63 r= ather than 255 and 254 as they were on Nehalem/Westmere? Is there formal documentatio= n you can point me at (from Intel perhaps?) that explains the official meth= od for discovering these PCI buses? -- John Baldwin
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